Go to the main menu
Skip to content
Go to bottom
REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
IEIE Transactions on Smart Processing and Computing
Journal Basic Information
Journal DOI :
The Institute of Electronics Engineers of Korea
Editor in Chief :
Volume & Issues
Volume 4, Issue 6 - Dec 2015
Volume 4, Issue 5 - Oct 2015
Volume 4, Issue 4 - Aug 2015
Volume 4, Issue 3 - Jun 2015
Volume 4, Issue 2 - Apr 2015
Volume 4, Issue 1 - Feb 2015
Selecting the target year
Real-time Ray-tracing Chip Architecture
Yoon, Hyung-Min ; Lee, Byoung-Ok ; Cheong, Cheol-Ho ; Hur, Jin-Suk ; Kim, Sang-Gon ; Chung, Woo-Nam ; Lee, Yong-Ho ; Park, Woo-Chan ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 2, 2015, Pages 65~70
DOI : 10.5573/IEIESPC.2015.4.2.065
In this paper, we describe the world's first real-time ray-tracing chip architecture. Ray-tracing technology generates high-quality 3D graphics images better than current rasterization technology by providing four essential light effects: shadow, reflection, refraction and transmission. The real-time ray-tracing chip named RayChip includes a real-time ray-tracing graphics processing unit and an accelerating tree-building unit. An ARM Ltd. central processing unit (CPU) and other peripherals are also included to support all processes of 3D graphics applications. Using the accelerating tree-building unit named RayTree to minimize the CPU load, the chip uses a low-end CPU and decreases both silicon area and power consumption. The evaluation results with RayChip show appropriate performance to support real-time ray tracing in high-definition (HD) resolution, while the rendered images are scaled to full HD resolution. The chip also integrates the Linux operating system and the familiar OpenGL for Embedded Systems application programming interface for easy application development.
80μW/MHz 0.68V Ultra Low-Power Variation-Tolerant Superscalar Dual-Core Application Processor
Kwon, Youngsu ; Lee, Jae-Jin ; Shin, Kyoung-Seon ; Han, Jin-Ho ; Byun, Kyung-Jin ; Eum, Nak-Woong ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 2, 2015, Pages 71~77
DOI : 10.5573/IEIESPC.2015.4.2.071
Upcoming ground-breaking applications for always-on tiny interconnected devices steadily demand two-fold features of processor cores: aggressively low power consumption and enhanced performance. We propose implementation of a novel superscalar low-power processor core with a low supply voltage. The core implements intra-core low-power microarchitecture with minimal performance degradation in instruction fetch, branch prediction, scheduling, and execution units. The inter-core lockstep not only detects malfunctions during low-voltage operation but also carries out software-based recovery. The chip incorporates a pair of cores, high-speed memory, and peripheral interfaces to be implemented with a 65nm node. The processor core consumes only 24mW at 350MHz and 0.68V, resulting in power efficiency of
. The operating frequency of the core reaches 850MHz at 1.2V.
Study of Cache Performance on GPGPU
Choi, Kyu Hyun ; Kim, Seon Wook ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 2, 2015, Pages 78~82
DOI : 10.5573/IEIESPC.2015.4.2.078
General-purpose graphics processing units (GPGPUs) provide tremendous computational and processing power. Despite the latency hiding mechanism, a GPU architecture requires high memory bandwidth and lower latency between computational units and the memory system. For this reason, the current GPU architecture has private L1 caches in each core and a shared L2 cache to increase performance by reducing memory latency. But in some cases, this CPU-like cache design is not suitable for GPGPUs. In this paper, we analyze detailed cache performance related to GPGPU application characteristics, and suggest technical alternatives for the GPGPU architecture as future work.
Core-A: A 32-bit Synthesizable Processor Core
Kim, Ji-Hoon ; Lee, Jong-Yeol ; Ki, Ando ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 2, 2015, Pages 83~88
DOI : 10.5573/IEIESPC.2015.4.2.083
Core-A is 32-bit synthesizable processor core with a unique instruction set architecture (ISA). In this paper, the Core-A ISA is introduced with discussion of useful features and the development environment, including the software tool chain and hardware on-chip debugger. Core-A is described using Verilog-HDL and can be customized for a given application and synthesized for an application-specific integrated circuit or field-programmable gate array target. Also, the GNU Compiler Collection has been ported to support Core-A, and various predesigned platforms are well equipped with the established design flow to speed up the hardware/software co-design for a Core-A-based system.
Review of Data-Driven Multivariate and Multiscale Methods
Park, Cheolsoo ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 2, 2015, Pages 89~96
DOI : 10.5573/IEIESPC.2015.4.2.089
In this paper, time-frequency analysis algorithms, empirical mode decomposition and local mean decomposition, are reviewed and their applications to nonlinear and nonstationary real-world data are discussed. In addition, their generic extensions to complex domain are addressed for the analysis of multichannel data. Simulations of these algorithms on synthetic data illustrate the fundamental structure of the algorithms and how they are designed for the analysis of nonlinear and nonstationary data. Applications of the complex version of the algorithms to the synthetic data also demonstrate the benefit of the algorithms for the accurate frequency decomposition of multichannel data.
Strong Uncorrelated Transform Applied to Spatially Distant Channel EEG Data
Kim, Youngjoo ; Park, Cheolsoo ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 2, 2015, Pages 97~102
DOI : 10.5573/IEIESPC.2015.4.2.097
In this paper, an extension of the standard common spatial pattern (CSP) algorithm using the strong uncorrelated transform (SUT) is used in order to extract the features for an accurate classification of the left- and right-hand motor imagery tasks. The algorithm is designed to analyze the complex data, which can preserve the additional information of the relationship between the two electroencephalogram (EEG) data from distant channels. This is based on the fact that distant regions of the brain are spatially distributed spatially and related, as in a network. The real-world left- and right-hand motor imagery EEG data was acquired through the Physionet database and the support vector machine (SVM) was used as a classifier to test the proposed method. The results showed that extracting the features of the pair-wise channel data using the strong uncorrelated transform complex common spatial pattern (SUTCCSP) provides a higher classification rate compared to the standard CSP algorithm.
Time-Frequency Analysis of Electrohysterogram for Classification of Term and Preterm Birth
Ryu, Jiwoo ; Park, Cheolsoo ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 2, 2015, Pages 103~109
DOI : 10.5573/IEIESPC.2015.4.2.103
In this paper, a novel method for the classification of term and preterm birth is proposed based on time-frequency analysis of electrohysterogram (EHG) using multivariate empirical mode decomposition (MEMD). EHG is a promising study for preterm birth prediction, because it is low-cost and accurate compared to other preterm birth prediction methods, such as tocodynamometry (TOCO). Previous studies on preterm birth prediction applied prefilterings based on Fourier analysis of an EHG, followed by feature extraction and classification, even though Fourier analysis is suboptimal to biomedical signals, such as EHG, because of its nonlinearity and nonstationarity. Therefore, the proposed method applies prefiltering based on MEMD instead of Fourier-based prefilters before extracting the sample entropy feature and classifying the term and preterm birth groups. For the evaluation, the Physionet term-preterm EHG database was used where the proposed method and Fourier prefiltering-based method were adopted for comparative study. The result showed that the area under curve (AUC) of the receiver operating characteristic (ROC) was increased by 0.0351 when MEMD was used instead of the Fourier-based prefilter.
A Novel Approach for Object Detection in Illuminated and Occluded Video Sequences Using Visual Information with Object Feature Estimation
Sharma, Kajal ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 2, 2015, Pages 110~114
DOI : 10.5573/IEIESPC.2015.4.2.110
This paper reports a novel object-detection technique in video sequences. The proposed algorithm consists of detection of objects in illuminated and occluded videos by using object features and a neural network technique. It consists of two functional modules: region-based object feature extraction and continuous detection of objects in video sequences with region features. This scheme is proposed as an enhancement of the Lowe's scale-invariant feature transform (SIFT) object detection method. This technique solved the high computation time problem of feature generation in the SIFT method. The improvement is achieved by region-based feature classification in the objects to be detected; optimal neural network-based feature reduction is presented in order to reduce the object region feature dataset with winner pixel estimation between the video frames of the video sequence. Simulation results show that the proposed scheme achieves better overall performance than other object detection techniques, and region-based feature detection is faster in comparison to other recent techniques.
Trust Predicated Routing Framework with Optimized Cluster Head Selection using Cuckoo Search Algorithm for MANET
Sekhar, J. Chandra ; Prasad, Ramineni Sivarama ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 2, 2015, Pages 115~125
DOI : 10.5573/IEIESPC.2015.4.2.115
This paper presents a Cuckoo search algorithm to secure adversaries misdirecting multi-hop routing in Mobile ad hoc networks (MANETs) using a robust Trust Predicated Routing Framework with an optimized cluster head selection. The clustering technique designed in this framework leads to efficient routing in MANETs. The heavy work load in the node causes an energy drop in cluster head, which leads to re-clustering of the group, and another cluster head is selected to avoid packet loss during data transmission. The problem in the re-clustering process is that the overall efficiency of the routing process is reduced and the processing time is increased. A Cuckoo search based optimization algorithm is proposed to solve the problem of re-clustering by selecting the secondary cluster head within the initially formed cluster group and eliminating the reclustering process. The proposed framework enables a node to select a reliable and secure route for MANET and the performance can be evaluated by comparing the simulated results with the AODV routing protocol, which shows that the performance of the proposed routing protocol are improved significantly.
Battery State-of-Charge Estimation Algorithm Using Dynamic Terminal Voltage Measurement
Lee, Su-Hyeok ; Lee, Seong-Won ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 2, 2015, Pages 126~131
DOI : 10.5573/IEIESPC.2015.4.2.126
When a battery is discharging, the battery's current and terminal voltage must both be measured to estimate its state of charge (SOC). If the SOC can be estimated by using only the current or voltage, hardware costs will decrease. This paper proposes an SOC estimation algorithm that needs to measure only the terminal voltage while a battery is discharging. The battery's SOC can be deduced from its open circuit voltage (OCV) through the relationship between SOC and OCV. But when the battery is discharging, it is not possible to measure the OCV due to the voltage drop in the battery's internal resistance (IRdrop). The proposed algorithm calculates OCV by estimating IRdrop using a dynamic terminal voltage measurement. This paper confirms the results of applying the algorithm in a hardware environment via algorithm binarization. To evaluate the algorithm, a Simulink battery model based on actual values was used.