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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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IEIE Transactions on Smart Processing and Computing
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The Institute of Electronics Engineers of Korea
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Volume & Issues
Volume 4, Issue 6 - Dec 2015
Volume 4, Issue 5 - Oct 2015
Volume 4, Issue 4 - Aug 2015
Volume 4, Issue 3 - Jun 2015
Volume 4, Issue 2 - Apr 2015
Volume 4, Issue 1 - Feb 2015
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Power-Efficient Wireless Neural Stimulating System Design for Implantable Medical Devices
Lee, Hyung-Min ; Ghovanloo, Maysam ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 3, 2015, Pages 133~140
DOI : 10.5573/IEIESPC.2015.4.3.133
Neural stimulating implantable medical devices (IMDs) have been widely used to treat neurological diseases or interface with sensory feedback for amputees or patients suffering from severe paralysis. More recent IMDs, such as retinal implants or brain-computer interfaces, demand higher performance to enable sophisticated therapies, while consuming power at higher orders of magnitude to handle more functions on a larger scale at higher rates, which limits the ability to supply the IMDs with primary batteries. Inductive power transmission across the skin is a viable solution to power up an IMD, while it demands high power efficiencies at every power delivery stage for safe and effective stimulation without increasing the surrounding tissue's temperature. This paper reviews various wireless neural stimulating systems and their power management techniques to maximize IMD power efficiency. We also explore both wireless electrical and optical stimulation mechanisms and their power requirements in implantable neural interface applications.
A Stability-Secured Loop Bandwidth Controllable Frequency Synthesizer for Multi-Band Mobile DTV Tuners
Kim, Kyeong-Woo ; Akram, Muhammad Abrar ; Hwang, In-Chul ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 3, 2015, Pages 141~144
DOI : 10.5573/IEIESPC.2015.4.3.141
A broadband radio frequency synthesizer for multi-band, multi-standard mobile DTV tuners is proposed, it's loop bandwidth can be calibrated to optimize integrated phase noise performance without the problem of phase noise peaking. For this purpose, we proposed a new third-order scalable loop filter and a scalable charge pump circuit to minimize the variation in phase margin during calibration. The prototype phase-lock loop is fabricated in 180nm complementary metal-oxide semiconductor shows that it effectively prevents phase noise peaking from growing while the loop bandwidth increases by up to three times.
A Multi-bit VCO-based Linear Quantizer with Frequency-to-current Feedback using a Switched-capacitor Structure
Park, Sangyong ; Ryu, Hyuk ; Sung, Eun-Taek ; Baek, Donghyun ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 3, 2015, Pages 145~148
DOI : 10.5573/IEIESPC.2015.4.3.145
In this letter, we present a new linearization method for a voltage controlled oscillator (VCO)-based quantizer in an analog-to-digital converter (ADC). The nonlinearity of the VCO generates unwanted harmonic spurs and reduces the signal-to-noise and distortion ratio (SNDR) of the VCO-based quantizer. This letter suggests a frequency-to-current feedback method to effectively suppress harmonic distortion. The proposed method decreases the harmonic spurs by more than 53 dB. And a VCO-based quantizer employing the proposed linearization method achieves a high SNDR of 74.1 dB.
A Capacitively Coupled Multi-Stage LC Oscillator
Park, Cheonwi ; Park, Junyoung ; Lee, Byung-Geun ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 3, 2015, Pages 149~151
DOI : 10.5573/IEIESPC.2015.4.3.149
Coupling with a ring of capacitors introduces in-phase coupling current in multi-stage LC oscillators, increasing coupling strength and phase spacing accuracy. Capacitive coupling is effective at high-frequency applications because it increases coupling strength with the operating frequency. However, capacitive loading from the ring lowers operating frequency and reduces the tuning range. Mathematical expressions of phase noise and phase spacing accuracy with capacitive coupling are examined here, and transistor-level simulations confirm the effectiveness of the capacitive coupling.
A Capacitor-less Low Dropout Regulator for Enhanced Power Supply Rejection
Yun, Seong Jin ; Kim, Jeong Seok ; Jeong, Taikyeong Ted. ; Kim, Yong Sin ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 3, 2015, Pages 152~157
DOI : 10.5573/IEIESPC.2015.4.3.152
Various power supply noise sources in a system integrated circuit degrade the performance of a low dropout (LDO) regulator. In this paper, a capacitor-less low dropout regulator for enhanced power supply rejection is proposed to provide good power supply rejection (PSR) performance. The proposed scheme is implemented by an additional capacitor at a gate node of a pass transistor. Simulation results show that the PSR performance of the proposed LDO regulator depends on the capacitance value at the gate node of the pass transistor, that it can be maximized, and that it outperforms a conventional LDO regulator.
Low Phase Noise CMOS VCO with Hybrid Inductor
Ryu, Seonghan ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 3, 2015, Pages 158~162
DOI : 10.5573/IEIESPC.2015.4.3.158
A low phase noise CMOS voltage controlled oscillator(VCO) for multi-band/multi-standard RF Transceivers is presented. For both wide tunability and low phase noise characteristics, Hybrid inductor which uses both bondwire inductor and planar spiral inductor in the same area, is proposed. This approach reduces inductance variation and presents high quality factor without custom-designed single-turn inductor occupying large area, which improves phase noise and tuning range characteristics without additional area loss. An LC VCO is designed in a 0.13um CMOS technology to demonstrate the hybrid inductor concept. The measured phase noise is -121dBc/Hz at 400KHz offset and -142dBc/Hz at 3MHz offset from a 900MHz carrier frequency after divider. The tuning range of about 28%(3.15 to 4.18GHz) is measured. The VCO consumes 7.5mA from 1.3V supply and meets the requirements for GSM/EDGE and WCDMA standard.
On Reducing False Positives of a Bloom Filter in Trie-Based Algorithms
Mun, Ju Hyoung ; Lim, Hyesook ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 3, 2015, Pages 163~168
DOI : 10.5573/IEIESPC.2015.4.3.163
Many IP address lookup approaches employ Bloom filters to obtain a high-speed search performance. Especially, it has been recently studied that the search performance of trie-based algorithms can be significantly improved by adding Bloom filters. In such algorithms, the number of trie accesses can be greatly reduced because Bloom filters can determine whether a node exists in a trie without actually accessing the trie. Bloom filters do not have false negatives but have false positives. False positives can lead to unnecessary trie accesses. The false positive rate must thus be reduced to enhance the performance of lookup algorithms applying Bloom filters. One important characteristic of trie-based algorithms is that all the ancestors of a node are also stored. The proposed algorithm utilizes this characteristic in reducing the false positive rate of a Bloom filter without increasing the size of the memory for the Bloom filter. When a Bloom filter produces a positive result for a node of a trie, we propose to check whether the ancestors of the node are also positives. Because Bloom filters have no false negatives, the negatives of any of the ancestors mean that the positive of the node is false. In other words, we propose to use more Bloom filter queries to reduce the false positive rate of a Bloom filter in trie-based algorithms. Simulation results show that querying one ancestor of a node can reduce the false positive rate by up to 67% with exactly the same architecture and the same memory requirement. The proposed approach can be applied to other trie-based algorithms employing Bloom filters.
DEX2C: Translation of Dalvik Bytecodes into C Code and its Interface in a Dalvik VM
Kim, Minseong ; Han, Youngsun ; Cho, Myeongjin ; Park, Chanhyun ; Kim, Seon Wook ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 3, 2015, Pages 169~172
DOI : 10.5573/IEIESPC.2015.4.3.169
Dalvik is a virtual machine (VM) that is designed to run Java-based Android applications. A trace-based just-in-time (JIT) compilation technique is currently employed to improve performance of the Dalvik VM. However, due to runtime compilation overhead, the trace-based JIT compiler provides only a few simple optimizations. Moreover, because each trace contains only a few instructions, the trace-based JIT compiler inherently exploits fewer optimization and parallelization opportunities than a method-based JIT compiler that compiles method-by-method. So we propose a new method-based JIT compiler, named DEX2C, in order to improve performance by finding more opportunities for both optimization and parallelization in Android applications. We employ C code as an intermediate product in order to find more optimization opportunities by using the GNU C Compiler (GCC), and we will detect parallelism by using the Intel C/C++ parallel compiler and the AESOP compiler in our future work. In this paper, we introduce our DEX2C compiler, which dynamically translates Dalvik bytecodes (DEX) into C code with method granularity. We also describe a new method-based JIT interface in the Dalvik VM for the DEX2C compiler. Our experiment results show that our compiler and its interface achieve significant performance improvement by up to 15.2 times and 3.7 times on average, in Element Benchmark, and up to 2.8 times for FFT in Smartbench.
Exploring Smartphone-Based Indoor Navigation: A QR Code Assistance-Based Approach
Chirakkal, Vinjohn V ; Park, Myungchul ; Han, Dong Seog ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 3, 2015, Pages 173~182
DOI : 10.5573/IEIESPC.2015.4.3.173
A real-time, Indoor navigation systems utilize ultra-wide band (UWB), radio-frequency identification (RFID) and received signal strength (RSS) techniques that encompass WiFi, FM, mobile communications, and other similar technologies. These systems typically require surplus infrastructure for their implementation, which results in significantly increased costs and complexity. Therefore, as a solution to reduce the level of cost and complexity, an inertial measurement unit (IMU) and quick response (QR) codes are utilized in this paper to facilitate navigation with the assistance of a smartphone. The QR code helps to compensate for errors caused by the pedestrian dead reckoning (PDR) algorithm, thereby providing more accurate localization. The proposed algorithm having IMU in conjunction with QR code shows an accuracy of 0.64 m which is higher than existing indoor navigation techniques.
A 10-bit 10MS/s differential straightforward SAR ADC
Rikan, Behnam Samadpoor ; Abbasizadeh, Hamed ; Lee, Dong-Soo ; Lee, Kang-Yoon ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 3, 2015, Pages 183~188
DOI : 10.5573/IEIESPC.2015.4.3.183
A 10-bit 10MS/s low power consumption successive approximation register (SAR) analog-to-digital converter (ADC) using a straightforward capacitive digital-to-analog converter (DAC) is presented in this paper. In the proposed capacitive DAC, switching is always straightforward, and its value is half of the peak-to-peak voltage in each step. Also the most significant bit (MSB) is decided without any switching power consumption. The application of the straightforward switching causes lower power consumption in the structure. The input is sampled at the bottom plate of the capacitor digital-to-analog converter (CDAC) as it provides better linearity and a higher effective number of bits. The comparator applies adaptive power control, which reduces the overall power consumption. The differential prototype SAR ADC was implemented with
complementary metal-oxide semiconductor (CMOS) technology and achieves an effective number of bits (ENOB) of 9.49 at a sampling frequency of 10MS/s. The structure consumes 0.522mW from a 1.8V supply. Signal to noise-plus-distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 59.5 dB and 67.1 dB and the figure of merit (FOM) is 95 fJ/conversion-step.
Design of a 12b SAR ADC for DMPPT Control in a Photovoltaic System
Rho, Sung-Chan ; Lim, Shin-Il ;
IEIE Transactions on Smart Processing and Computing, volume 4, issue 3, 2015, Pages 189~193
DOI : 10.5573/IEIESPC.2015.4.3.189
This paper provides the design techniques of a successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for distributed maximum power point tracking (DMPPT) control in a photovoltaic system. Both a top-plate sampling technique and a
-based switching technique are applied to the 12b capacitor digital-to-analog converter (CDAC). With these techniques, we can implement a 12b SAR ADC with a 10b capacitor array digital-to-analog converter (DAC). To enhance the accuracy of the ADC, a single-to-differential converted DAC is exploited with the dual sampling technique during top-plate sampling. Simulation results show that the proposed ADC can achieve a signal-to-noise plus distortion ratio (SNDR) of 70.8dB, a spurious free dynamic range (SFDR) of 83.3dB and an effective number of bits (ENOB) of 11.5b with bipolar CMOS LDMOD (BCDMOS)
technology. Total power consumption is 115uW under a supply voltage of 3.3V at a sampling frequency of 1.25MHz. And the figure of merit (FoM) is 32.68fJ/conversion-step.