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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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The Journal of Korean Institute of Communications and Information Sciences
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The Korean Institute of Communications and Information Sciences
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Volume & Issues
Volume 24, Issue 12B - Dec 1999
Volume 24, Issue 12A - Dec 1999
Volume 24, Issue 11A - Nov 1999
Volume 24, Issue 10B - Oct 1999
Volume 24, Issue 10A - Oct 1999
Volume 24, Issue 9B - Sep 1999
Volume 24, Issue 9A - Sep 1999
Volume 24, Issue 8B - Aug 1999
Volume 24, Issue 8A - Aug 1999
Volume 24, Issue 7B - Jul 1999
Volume 24, Issue 7A - Jul 1999
Volume 24, Issue 6B - Jun 1999
Volume 24, Issue 6A - Jun 1999
Volume 24, Issue 5B - 00 1999
Volume 24, Issue 5A - 00 1999
Volume 24, Issue 4B - 00 1999
Volume 24, Issue 4A - 00 1999
Volume 24, Issue 3B - 00 1999
Volume 24, Issue 3A - 00 1999
Volume 24, Issue 2B - 00 1999
Volume 24, Issue 2A - 00 1999
Volume 24, Issue 1B - 00 1999
Volume 24, Issue 1A - 00 1999
Volume 24, Issue 12 - 00 1999
Volume 24, Issue 11B - 00 1999
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A Handoff-Minimizing Call Connection Strategy in an Overlaid Macro-Micro CDMA Cellular System
Gang, Seong Min ; Kim, Jae Hun ; Cha, Dong Wan ;
The Journal of Korean Institute of Communications and Information Sciences, volume 24, issue 3A, 1999, Pages 341~341
In the future, to cope with the increasing demand for personal and mobile communications, a two-tier CDMA cellular system with microcells and overlaying macrocells is likely to be deployed. In this system, slow-moving mobile users are assigned to microcells and those who move fast are assigned to overlaying macrocells in order to minimize the total number of handoffs. With this consideration the problem is how to find the thresholds by which the system distinguishes fast-moving users from those who move slowly based on the estimated speed of users. In this paper, two methods for the mobile speed estimation are proposed and two operations schemes for micro-macro cellular CDMA system are suggested. Based on these, average traffic offered to microcells and macrocells is analyzed respectively. Optimization models to find the optimal thresholds for micro-macrocell selection, which are subject to the constrains of QoS, are developed in view of minimizing the weighted total number of handoffs. And then algorithms to find optimal solutions of the models are devised.
Impact of the Time Dispersion and Power Delay Profile Shape on the Performance of a Reverse Link CDMA PCS System
Jeong, Yeon Ho ;
The Journal of Korean Institute of Communications and Information Sciences, volume 24, issue 3A, 1999, Pages 352~352
this paper presents the impact of time dispersion and power delay profile shape on the performance of a reverse link direct sequence code division multiple access (DS/CDMA) system. A reverse link CDMA PCS simulator has been developed to observe the performance variation with respect to the time dispersion and power delay profile (PDP) shape. That is, time dispersion, the length and average attenuation of the main profile (the first 3 echoes) and the average attenuation of the second echo group have been considered. A total of 80 PDPs were applied to the simulator and the results show that unlike a TDMA-based system (e.g. GSM), delay spread does not show a good correlation with the performance. In fact, average delay is found to have better correlation with the system performance in a CDMA PCS system. In addition, among the factors related to the PDP shape, the performance appears more sensitive to the relative power level of the main profile.
VLSI Design of the PN Code Searcher Having the Energy Calcluator with a Sharable Architecture
Lee, Seong Ju ; Kim, Jae Seok ;
The Journal of Korean Institute of Communications and Information Sciences, volume 24, issue 3A, 1999, Pages 358~358
In this paper, we proposed a new hardware architecture of PN code searcher for CDMA mobile station in order to reduce the hardware complexity. The proposed PN code searcher has a energy calculation block which is shared by two correlators. Our system is designed suitable for IS-95 based CDMA PCS. The new architecture has been designed using VHDL and implemented on Altera FPGA chipset. The gate count is about 7,500 and the layout area is 2.13 ㎜×1.11 ㎜ by using 0.6㎛ CMOS library. The hardware complexity of our proposed architecture is decreased by 15% to be compared with the convention one.
The Call Control Scheme for Non-uniform Traffic Distribution in Multiple Cell Model
Seong, Hong Seok ; Im, Seung Cheol ; Lee, Dong Myeong ; Park, Dong Seon ;
The Journal of Korean Institute of Communications and Information Sciences, volume 24, issue 3A, 1999, Pages 367~367
In this paper, we propose the call control scheme which can improve the capacity of the whole system for the non-uniform traffic load distribution and the multiple types of services in multiple cell CDMA environments. In CDMA system, the number of mobile stations which can be served simultaneously in a base station is limited by the amount of total interference received. Further, the average number of mobile stations in each cell may not be uniformly distributed. Considering the facts, the call admission control method using the effective bandwidth concept is employed in this paper. The bandwidth for a new call is allocated by considering the number of mobile station being served and dynamically assigned by taking account of the blocking rate of new calls and the dropping rate of handoff calls. The call control procedure is experimented through a simulation study by dynamically assigning the bandwidth to new and handoff calls. The results show our proposed call control scheme can accommodate more mobile stations than the one of method.
Performance Analysis of Coherent Reverse Link WCDMA Systems Using Adaptive Array Antennas
Han, Jin Gyu ; Mun, Mun Cheol ; Jeong, Han Ok ; Yun, Yeong Jung ; Park, Han Gyu ;
The Journal of Korean Institute of Communications and Information Sciences, volume 24, issue 3A, 1999, Pages 374~374
Adaptive array antennas have emerged as a useful technique to enhance the cell capacity of mobile communications by maximizing the user signal and rejecting interferences. In this paper, the performance of the coherent reverse link CDMA systems using adaptive array antennas in base station is analyzed by the vector channel model in which the correlation between the fading signals received at each antennas is considered. Also chip-level simulator of IS-665 wideband CDMA modern is developed and the adaptive beamforming part is inserted to analyze the effect on the cell capacity by adaptive array antennas. The effect of path spatial diversity and trade off between beamforming and diversity is also discussed using 2D RAKE receiver structure.
Performance Analysis of Air Interface Signaling Protocol for Future Mobile Communication
Jin, Sang Min ; Park, Seong Su ; Song, Yeong Jae ; Jo, Dong Ho ; Song, Pyeong Jung ;
The Journal of Korean Institute of Communications and Information Sciences, volume 24, issue 3A, 1999, Pages 381~381
In order to derive the suitable protocol architecture for future mobile communication systems, we evaluate the processing performance of signalling messages in the separate protocol layer and combined protocol layer recommended by W-CDMA and cdma2000, respectively. Also, we evaluate the performance of combined processing and sequential processing method in the case of handling registration and authentication messages. According to simulation results, in the case that error occurs, separate protocol layer has better performance than combined protocol layer as error rate increase. because, although separate protocol layer retransmits only errored frame, but combined protocol layer retransmits two frame. On the other hand, in registration and authentication message processing, combined processing method that transmits two message simultaneously is better than sequential processing method because of transmission delay gain due to simultaneous transmission in the case that channel error rate is low. However, sequential processing method is better than combined processing method because of retransmission gain due to transmission error when channel error rate is high.
Channel Estimation Technique in a DS/CDMA with M-ary Orthogonal Modulation
Yun, Seok Hyeon ; Kim, Jin Il ; Gang, Seong Jin ; Gang, Chang Eon ;
The Journal of Korean Institute of Communications and Information Sciences, volume 24, issue 3A, 1999, Pages 391~391
The FPGA Implementation of A High Speed Modular Exponentiation Processor
Lee, Seong Sun ; Han, Seung Jo ;
The Journal of Korean Institute of Communications and Information Sciences, volume 24, issue 3A, 1999, Pages 398~398
In RSA crytosystem fast computation of modular exponentiation is essential for the efficient encryption and decryption since it requires the modular exponentiation of large integer prime numbers more than 512bits. In this paper, we design a high speed modular exponentiation processor which computes fast modular exponentiation with the carry save addition and the interleaved modular multiplication scheme which limits partial products by quotient estimation. It is modeled using VHDL by top-down design process based on automatic synthesis methodology. Synthesis and verification is then performed by using SYNOPSYS tools. Finally, we implement it with the XILINX XC4052XLPG411-3 FPGA, and present the test performance.
New Termination Algorithm of Turbo Codes with Small Interleaver Size
Choe, Hui Dong ; No, Jong Seon ; Gang, Hui Won ;
The Journal of Korean Institute of Communications and Information Sciences, volume 24, issue 3A, 1999, Pages 406~406
It is well-known that turbo codes have a good error correcting capability compared to other channel coding schemes. But its performance relies on the interleaver size of turbo encoder, i.e., frame size. In the case of voice transmission in a mobile communication environment, its frame sizes are very small, which degrades the performance of turbo codes. The probability of bit errors is high in the end of each frame for turbo code and it causes the performance degradation especially, for voice transmission with small frame size. In this paper, we propose the new termination algorithms of turbo codes suitable for small frame sizes and analyzed its performance with frame size of 24 and 192 bits by computer simulation.
Design of architecture for the High Speed Encryption Chip of Improved DES
Choe, Gwang Yun ; Jeong, Il Yong ; Han, Seung Jo ;
The Journal of Korean Institute of Communications and Information Sciences, volume 24, issue 3A, 1999, Pages 412~412
The Improved DEX algorithm had been published as a replacement to the Data Encryption Standard(DES) in  and . It has a key length of 112bits. The plaintext data consists of 96 bits divided into 3 sub-blocks with 32 bits. The Improved DES has a potentially higher resistance to differential cryptanalysis than the DES due to the asymmetric number of f functions performed on each of the 3 sub-blocks and due to the increase of S-boxes from 8 to 16.We have designed the Improved DES as hardware using the high-speed parallel pipeline structure first. And then we have performed the simulation of the ultra high-speed block cipher system described by VHDL. Designed hardware has parallel pipeline structure, pipeline depth is 83 step that is very large step. Therefore, the structure was compatible in large data or stream data communication network. As result of the simulation, we could got the high speed encryption chip of 33.33Gbps at the input pulse of 350MHz.
VLSI DESIGN OF MULTIPLER-ACCUMULATOR MACRO FOR DSP-ORIENTED RISC MICROPROCESSOR
Choe, Byeong Yun ;
The Journal of Korean Institute of Communications and Information Sciences, volume 24, issue 3A, 1999, Pages 421~421
This paper describes a on-chip multiplier-accumulator macro for 32-bit RISC microprocessor which is designed for control and DSP applications. To satisfy trade-off between fast multiplication and area-efficient hardware, multiplication scheme is adopted which can generate 64-bit carry-save results for 32-bit by 32-bit multiplication(MUL) or multiplication & accumulation(MAC) with repeated use of 32-bit by 8-bit dedicated multiplier hardware and then add carry-save results with on-chip 32-bit ALU. To consider characteristics that most data used in multiplication are small, early-termination hardware which has data-dependent multiplication cycles is included. This multiplier architecture uses modified booth's algorithm and adopts efficient sign-extension scheme which eliminate over-loading problem of sign-bit signal. This multiplier is designed with 0.6㎛ triple metal CMOS technology and consists of about 9,100 gates and its worst case delay is about 13.8ns and its layout size is 2.16㎜ * 1.34㎜.
International competitiveness of Korean Information and Telecommunication Industry
Ji, Gyeong Yong ; Gang, Sin Won ;
The Journal of Korean Institute of Communications and Information Sciences, volume 24, issue 3A, 1999, Pages 431~431
This study examines the international competitiveness of Korean information and telecommunication industry by suing competitiveness index such as the RCA index, the Trade Specialization index, and the Total Factor Productivity.The results of this study show that the industry's competitiveness slightly decreases since 1995, but not the Total Factor Productivity. In conclusion, the industry keeps the competitiveness over all. Therefore, to keep or improve the competitiveness continuously, the industry is required the government's intensive investment and administrative support. And the industry should bring up by venture and small & medium size enterprise to have great economic impacts to the other industries. Also, the increasing production and export promoting policy will be grown the industry and improved nation's the balance of trade.
A Study on the Proxy signatures for Partial Delegation with Warrant
Kim, Seung Ju ; Park, Sang Jun ; Yang, Hyeong Gyu ; Won, Dong Ho ;
The Journal of Korean Institute of Communications and Information Sciences, volume 24, issue 3A, 1999, Pages 439~439
Proxy signatures, introduced by Mambo, Usuda and Okamoto allow a designated person to sign on behalf of an original signer. This paper first presents a new type of digital proxy signatures called partial delegation with warrant. Proxy signatures for partial delegation with warrant combine the benefit of Mambo's partial delegation and Neuman's delegation by warrant. Moreover, we also propose straightforward and concrete proxy signature schemes satisfying our conditions.
Efficient Electronic Cash System Based on Randomized Blind Signature
Choe, Yeong Cheol ; Kim, Seung Ju ; Won, Dong Ho ;
The Journal of Korean Institute of Communications and Information Sciences, volume 24, issue 3A, 1999, Pages 447~447
N.Ferguson presented an efficient electronic cash system based on a randomized blind signature at Eurocrypt'93. Ferguson's system played an important role to solve the problem that is to have much overhead of communication, which is the worst problem in electronic cash system until that time, using the challenge-and-response technique. But his system has a fatal problem that breaks the security requirement, which is the one of basic requirements in the electronic cash system. That is, if a bank, the issuer of electronic cash, colludes with a shop, the participant of electronic cash system, it could frame up an honest user as a double-spender by collusion attack. This problem make the electronic cash system to have no legal force. In this paper, we analyze the problem of Ferguson's system and propose the countermeasures against it.