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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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The Journal of Korean Institute of Communications and Information Sciences
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The Korean Institute of Communications and Information Sciences
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Volume & Issues
Volume 27, Issue 12C - Dec 2002
Volume 27, Issue 11C - Nov 2002
Volume 27, Issue 10C - Oct 2002
Volume 27, Issue 10A - Oct 2002
Volume 27, Issue 9C - Sep 2002
Volume 27, Issue 8C - Aug 2002
Volume 27, Issue 8B - Aug 2002
Volume 27, Issue 8A - Aug 2002
Volume 27, Issue 7C - Jul 2002
Volume 27, Issue 7B - Jul 2002
Volume 27, Issue 7A - Jul 2002
Volume 27, Issue 6C - Jun 2002
Volume 27, Issue 6B - Jun 2002
Volume 27, Issue 6A - Jun 2002
Volume 27, Issue 5C - May 2002
Volume 27, Issue 4C - Apr 2002
Volume 27, Issue 4B - Apr 2002
Volume 27, Issue 4A - Apr 2002
Volume 27, Issue 3C - Mar 2002
Volume 27, Issue 3B - Mar 2002
Volume 27, Issue 3A - Mar 2002
Volume 27, Issue 2B - Feb 2002
Volume 27, Issue 2A - Feb 2002
Volume 27, Issue 2C - Jan 2002
Volume 27, Issue 1C - Jan 2002
Volume 27, Issue 1B - Jan 2002
Volume 27, Issue 1A - Jan 2002
Volume 27, Issue 9 - 00 2002
Volume 27, Issue 8 - 00 2002
Volume 27, Issue 3 - 00 2002
Volume 27, Issue 12 - 00 2002
Volume 27, Issue 11 - 00 2002
Volume 27, Issue 10 - 00 2002
Selecting the target year
Case study of the large switching software metrics and their fault analysis
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 10C, 2002, Pages 887~901
Software management model divided into the software project model and design estimation model, software matrices model, reliability growth model, process improvement model(or process maturity model) etc. Among these software management models, software complexity model make an estimated of the product software. For a practice of software managed, need to guideline of the static analysis of software. Especially, Software complexity model introduced for the estimation of software quantity and program complexity. In case of measurement the software matrices, its need for us to analysis of software quality and products. On the other hand, we known that complexity program include many defects and consuming of source cost. So, we apply to complexity model using of the program complexity, control structure and volume matrices, interface metrics, process complexity metrics method. In this paper, we represent that the analysis of fault data detected during the system test. Also, we analysis of program control structure and interface, volume matrices in various aspect of switching software. Others, their results utilized similar of project and system development.
Maintaining Robust Spanning Tree in Wireless Ad-hoc Network Environments
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 10C, 2002, Pages 902~911
A wireless ad-hoc network is a collection of wireless mobile hosts forming a temporary network without the aid of any centralized adminstration or standard support services. Wireless ad-hoc networks may be quite useful in that they can be instantly deployable and resilient to change. In this environment, for many crucial distributed applications, it is necessary to design robust virtual infrastructures that are fault-tolerant, self-stabilized, and resource-efficient. For this task this paper proposes a scheme of maintaining robust spanning trees which are little affected by topological changes. By maintaining such a spanning tree and adapting it to the environments with frequent topological changes, one can improve the reliability and efficiency of many applications that use the spanning tree.
A Study on a Solid Modeler for Web-based Collaborative Design
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 10C, 2002, Pages 912~920
As computer systems and communication technologies develop rapidly, CSCW(Computer Supported Collaborative Work) system appears nowadays, through which it is available to work on virtual space without any restriction of time and place. Most of CWCS systems depend on a special network and groupware. The systems of graphics and CAD are not so many because they are specified by hardware and application software. We propose a Web-based collaborative CAD system which is independent from any platforms, and develop a 3D solid modeler in the system. This system can be worked in the environment of Client/Server architecture. Clients connect to the design server through Java applet on WWW. The server is implemented by Java application.
A New Techno-Economic Analysis for Developing an Effective Maintenance Policy of Telecommunication Systems
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 10C, 2002, Pages 921~932
In this research, we seek to identify an effective operation management strategy of telecommunication systems. In order to develop operation management strategies, we implement a quantitative techno-economic analysis. We evaluate related issues and factors, and apply the developed method to PSTN switching systems. In the proposed techno-economic modeling, we apply a well-known factor analysis technique-analytic hierarchy process-to evaluate PSTN operation management strategies. Then, we implement a decision analysis methodology to evaluate the cost of proposed strategies. We evaluate the proposed methodology by using available real data of the PSTN system. The primary impact of this research will be realized in helping PSTN operator select the best operation management strategy of PSTN system.
A study on the Protection/Restoration of High speed Ethernet in Optics Layer
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 10C, 2002, Pages 933~936
One of the problems of a Gigabit-Ethernet system for installation in telecom networks is its relative low reliability compared with SONET, the major telecom network system, which restores from fault within 50 msec. In this study, an optics layer protection for the Gigabit-Ethernet system is proposed. It monitors optical signal quality by comparing the signal level with a calibrated window, and switchs fibers within a time comparable to SONET.
A Photonic Packet Switch for Wavelength-Division Mdltiplexed Networks
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 10C, 2002, Pages 937~944
The current fast-growing Internet traffic is demanding more and more network capacity. Photonic packet switching offers high-speed, data rate/format transparency, and configurability, which are some of the important characteristics needed in future networks supporting different forms of data. In this paper, we define that optical backbone networks for IP transport consist of optical packet core switches and optical fibers. We propose a multi-link photonic packet switch managing as single media which unifies the whole bandwidth of multiple wavelengths on the optical fiber in the WDM optical networks. The proposed switch uses optical packet memories of output link equally as well as using the WDM buffer. So it cuts down the required number of buffers and realizes of the optical packet memory economically.
Performance Relation Analysis of CLR, Buffer Capacity and Delay Time in the ATM Access Node
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 10C, 2002, Pages 945~950
In this paper the performance evaluations on Asynchronous Transfer Mode(ATM) access node are performed in the ATM access network which consists of access node and channel. The performance factors of access node are Cell Loss Ratio(CLR), buffer capacity and delay time. Both the ATM cell-scale queueing model and burst-scale queueing model are considered as the traffic model of access node for various traffic types such as Constant Bit Rate(CBR), Variable Bit Rate(VBR) and random traffic in the ATM access networks. Based on these situations, the relation of CLR, buffer capacity and delay time is analyzed in the ATM access node.
Synchronization for VDSL system using DMT
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 10C, 2002, Pages 951~962
A DMT transceiver recovers the sampling time from reserved sub-carriers, the pilots. Since the pilots are available after the FFT, the symbol synchronization must be done before sample synchronization. In DMT VDSL system, symbol synchronization is handled separately from sample synchronization, although the two processes are intimately related. The DMT symbol itself contains sufficient information, the cyclic extension, for symbol synchronization. Using only the sign bit of received signal, the Maximum Likelihood Estimation solution is derived. The Tx windowing in the transmitter of DMT VDSL system results in the blurring of MLE peaks. We propose the weighted summing MLE method using the sign bit which produces the clearly sharp top of MLE peaks. The stability of symbol synchronization is improved significantly by averaging over a few symbols. This paper presents the study of the original MLE and the weighted summing MLE using sign bit. A clock difference between transmitter and receiver destroys the oahogonality of the carriers. Therefore, a receiver using asynchronous sampling must perform timing correction in the discrete-time domain. We introduce an efficient digital sample synchronization method which is based on temporal and frequency domain digital signal processing.
A 8192-point pipelined FFT/IFFT processor using two-step convergent block floating-point scaling technique
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 10C, 2002, Pages 963~972
An 8192-point pipelined FFT/IFFT processor core is designed, which can be used in multi-carrier modulation systems such as DUf-based VDSL modem and OFDM-based DVB system. In order to improve the signal-to-quantization-noise ratio (SQNR) of FFT/IFFT results, two-step convergent block floating-point (TS_CBFP) scaling is employed. Since the proposed TS_CBFP scaling does not require additional buffer memory, it reduces memory as much as about 80% when compared with conventional CBFP methods, resulting in area-and power-efficient implementation. The SQNR of about 60-㏈ is achieved with 10-bit input, 14-bit internal data and twiddle factors, and 16-bit output. The core synthesized using 0.25-
CMOS library has about 76,300 gates, 390K bits RAM, and twiddle factor ROM of 39K bits. Simulation results show that it can safely operate up to 50-㎒ clock frequency at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-
. It was verified by Xilinx FPGA implementation.
Fast-Serial Finite Field Multiplier without increasing the number of registers
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 10C, 2002, Pages 973~979
In this paper, an efficient architecture for the finite field multiplier is proposed. This architecture is faster and smaller than any other LFSR architectures. The traditional LFSR architecture needs t x m registers for achieving the t times speed. But, we designed the multiplier using a novel fast architecture without increasing the number of registers. The proposed multiplier is verified with a VHDL description using SYNOPSYS simulator. The measured results show that the proposed multiplier is 2 times faster than the serial LFSR multiplier. The proposed multiplier is expected to become even more advantageous in the smart card cryptography processors.
ASIC Implementation of Synchronization Circuit with Lossless Data Compensation
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 10C, 2002, Pages 980~986
In the fast data communication system, synchronized by a clock source, the loss of data will often occur due to several reasons as a differential routing path between data and clock, a differential propagation delay of components or an unstable phase of clock and data by external noise. In this paper, we describe the ASIC implementation of the data compensation circuit which can detect the data loss from above problems and recovery to original data with stable synchronization. Especially it supports a strong stability and a good BER in the communication system for fast data transfer as optic area. This circuit is implemented by Verilog HDL and available to the digital ASIC implementations related to fast data transfer.
Giga-bps CMOS Clock and Data Recovery Circuit with a novel Adaptive Phase Detector
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 10C, 2002, Pages 987~992
In this paper, a new clock and data recovery circuit is proposed for the application of data communication systems requiring ㎓-range clock signals. The circuit is suitable for recovering NRZ data which is widely used for high speed data transmission in ㎓ ranges. The high frequency jitter is one of major performance-limiting factors in PLL, particularly when NRZ data patterns are used. A novel phase detector is able to suppress this noise, and stable clock generation is achieved. Futhermore, the phase detector has an adaptive delay cell removing the dead zone problem and has the optimal characteristics for fast locking. The proposed circuit has a convenience structure that can be easily extended to multi-channels. The circuit is designed based on CMOS 0.25㎛ fabrication process and verified by measurement result.
A Study of Predistorter using schottkey diode for Power Amplifier
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 10C, 2002, Pages 993~998
At Power amplifier, distortion of output is appeared because of non-linearlity, so we must study method of compensation for non-linearity. In this paper, it was studied about the characteristic of predistorter using serial schottky diode for an amplifier. As a result, we confirmed that power amplifier was able to linearize when we put predistorter using non-linearity of schottky diode before power amplifier. When input carrier level was low, input carrier was delivered directly into power amplifier but input carrier level was high, input carrier was delivered into power amplifier through predistorter with suppressed level. As a result power amplifier always was at saturation region. Through simulation using serenade 8.0, we have concluded that efficiency was improved about 3%, and predistorter got best linearity at 1.8㎓ between 800㎒∼2.2㎓.
A High-Speed Matched Filter for Searching Synchronization in DSSS Receiver
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 10C, 2002, Pages 999~1007
In this paper, the operation of matched filter for searching initial synchronization in direct sequence spread spectrum receiver is studied. The implementation model of the matched filter by HDL (Hardware Description Language) is proposed. The model has an architecture based on parallelism and pipeline for fast processing, which includes circular buffer, multiplier, adder, and code look-up table. The performance of the model is analyzed and compared with the implementation by a conventional digital signal processor. It is implemented on a FPGA (Field Programmable Gate Array) and its operation is validated in a timing simulation result.
Implementation of Multiplierless Interpolation FIR Filters for IMT-2000 Systems
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 10C, 2002, Pages 1008~1014
This paper is concerned about multiplierless interpolation FIR filters. In this paper, we propose a filter that performs T tap 1:N interpolation FIR filter operation with B-bit inputs without using multipliers. This is done by applying a method which converts a 2s complement multi-bits input to multiple single-bit inputs and a lookup table minimization method which reduces the size of lookup tables by use of the symmetry of filter coefficients and the symmetry of each lookup table. Two FIR filters are implemented using the methods proposed in this paper. Each of the two filters respectively follows the two design parameters in the specification of IMT-2000. Those two FIR filters have an advantage that the number of required gates is reduced up to 70% comparing to that of a conventional transversal FIR filter.
The Design and Implementation of Access Control framework for Collaborative System
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 10C, 2002, Pages 1015~1026
As per increasing research interest in the field of collaborative computing in recent year, the importance of security issues on that area is also incrementally growing. Generally, the persistency of collaborative system is facilitated with conventional authentication and cryptography schemes. It is however, hard to meet the access control requirements of distributed collaborative computing environments by means of merely apply the existing access control mechanisms. The distributed collaborative system must consider the network openness, and various type of subjects and objects while, the existing access control schemes consider only some of the access control elements such as identity, rule, and role. However, this may cause the state of security level alteration phenomenon. In order to handle proper access control in collaborative system, various types of access control elements such as identity, role, group, degree of security, degree of integrity, and permission should be taken into account. Futhermore, if we simply define all the necessary access control elements to implement access control algorithm, then collaborative system consequently should consider too many available objects which in consequence, may lead drastic degradation of system performance. In order to improve the state problems, we propose a novel access control framework that is suitable for the distributed collaborative computing environments. The proposed scheme defines several different types of object elements for the accessed objects and subjects, and use them to implement access control which allows us to guarantee more solid access control. Futhermore, the objects are distinguished by three categories based on the characteristics of the object elements, and the proposed algorithm is implemented by the classified objects which lead to improve the systems' performance. Also, the proposed method can support scalability compared to the conventional one. Our simulation study shows that the performance results are almost similar to the two cases; one for the collaborative system has the proposed access control scheme, and the other for it has not.
A Design and Implementation of the Power Amplifier using Linearizer for PCS
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 10C, 2002, Pages 1027~1031
In this paper, the non linear characteristics of HPA (High Power Amplifier) is improved by using predistorter. Predistorter consists of 0 degree and 90 degree couplers, complementary amplifier, shottky diodes, and attenuators. Gain of the Linearized HPA is 54㏈ at 1960㎒ - 1980㎒. IMD (Inter Modulation Distortion) characteristic shows -58㏈c at 39㏈m/tone ⓐ1.23㎒. The IMD performance of this predistorter is improved by 14㏈.