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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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The Journal of Korean Institute of Communications and Information Sciences
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The Korean Institute of Communications and Information Sciences
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Volume & Issues
Volume 27, Issue 12C - Dec 2002
Volume 27, Issue 11C - Nov 2002
Volume 27, Issue 10C - Oct 2002
Volume 27, Issue 10A - Oct 2002
Volume 27, Issue 9C - Sep 2002
Volume 27, Issue 8C - Aug 2002
Volume 27, Issue 8B - Aug 2002
Volume 27, Issue 8A - Aug 2002
Volume 27, Issue 7C - Jul 2002
Volume 27, Issue 7B - Jul 2002
Volume 27, Issue 7A - Jul 2002
Volume 27, Issue 6C - Jun 2002
Volume 27, Issue 6B - Jun 2002
Volume 27, Issue 6A - Jun 2002
Volume 27, Issue 5C - May 2002
Volume 27, Issue 4C - Apr 2002
Volume 27, Issue 4B - Apr 2002
Volume 27, Issue 4A - Apr 2002
Volume 27, Issue 3C - Mar 2002
Volume 27, Issue 3B - Mar 2002
Volume 27, Issue 3A - Mar 2002
Volume 27, Issue 2B - Feb 2002
Volume 27, Issue 2A - Feb 2002
Volume 27, Issue 2C - Jan 2002
Volume 27, Issue 1C - Jan 2002
Volume 27, Issue 1B - Jan 2002
Volume 27, Issue 1A - Jan 2002
Volume 27, Issue 9 - 00 2002
Volume 27, Issue 8 - 00 2002
Volume 27, Issue 3 - 00 2002
Volume 27, Issue 12 - 00 2002
Volume 27, Issue 11 - 00 2002
Volume 27, Issue 10 - 00 2002
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Web Proxy Cache Replacement Algorithms using Object Type Partition
Soo-haeng, Lee ; Sang-bang, Choi ;
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 5C, 2002, Pages 399~410
Web cache, which is functionally another word of proxy server, is located between client and server. Web cache has a limited storage area although it has broad bandwidth between client and proxy server, which are usually connected through LAN. Because of limited storage capacity, existing objects in web cache can be deleted for new objects by some rules called replacement algorithm. Hit rate and byte-hit rate are general metrics to evaluate replacement algorithms. Most of the replacement algorithms do satisfy only one metric, or sometimes none of them. In this paper, we propose two replacement algorithms to achieve both high hit rate and byte-hit rate with great satisfaction. In the first algorithm, the cache is appropriately partitioned according to file types as a basic model. In the second algorithm, the cache is composed of two levels; the upper level cache is managed by the basic algorithm, but the lower level is collectively used for all types of files as a shared area. To show the performance of the proposed algorithms, we evaluate hit rate and byte-hit rate of the proposed replacement algorithms using the trace driven simulation.
A New Survivor Path Memory Management Method for High-speed Viterbi Decoders
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 5C, 2002, Pages 411~421
In this paper, we present a new survivor path memory management method and a dedicated hardware architecture for the design of high-speed Viterbi decoders in modern digital communication systems. In the proposed method, a novel use of k-starting node number deciding circuits enables to acheive the immediate traceback of the merged survivor path from which we can decode output bits, and results in smaller survivor path memory size and processing delay time than the previously known methods. Also, in the proposed method, the survivor path memory can be constructed with ease using a simple standard dual-ported memory since one read-pointer and one write-pointer, that are updated at the same rate, are required for managing the survivor path: the previously known algorithms require either complex k-ported memory structure or k-times faster read capability than write. With a moderate hardware cost for immediate traceback capability the proposed method is superior to the previously known methods for high-speed Viterbi decoding.
Fiber-Optic Network Design Supporting Network Survivability
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 5C, 2002, Pages 422~434
We propose 3-layered hierarchical fiber-optic backbone transmission network composed of B-DCS, Backbone ring, Edge ring for efficient transmission of high capacity traffic and consider design method to ensure network survivability of each layer at affordable cost. Mathematical ring-construction cost minimization using MIP(Mixed Integer Programming) models results in NP-complete problem. So, it is hard to solve it within reasonable computing time. on a large-scale network. Therefore we develop heuristic algorithms solving WSCAP(Working and Spared Channel Assignment Problem) for B-DCS, MRLB(Multi-Ring Load Balancing) problem for Backbone ring, and ORLB(Overlayed Ring Load Balancing) problem for Edge ring and show their usefulness through case study.
Packet scheduling algorithm for guaranteed bound and firewall property of delay performance
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 5C, 2002, Pages 435~444
In this paper, a novel packet scheduling algorithm, so-called the CSL algorithm is discussed, whereby the firewall property as well as the deterministic delay bound guarantee are supported in session level. Lots of simulation studies validate those properties of the CSL algorithm. The CSL algorithm is distingushable from the well- known EDD scheme in terms of the firewall property. Regarding the implementation complexity, the CSL algorithm turns out to be of 0(1) besides the sorting overhead. Owing to the maintained generic fair queueing structure in the CSL algorithm, a various fair queueing schemes can be applied with minor modification. For the TCP/IP network which is vulnerable to the misbehaving traffic sources, the firewall property of the CSL algorithm is quite useful for the advanced quality of services.
Real-Time Traffic Connection Admission Control of Queue Service Discipline
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 5C, 2002, Pages 445~453
We propose a cell-multiplexing scheme for the real-time communication service in ATM network and a new service discipline guarantee end-to-end delay based on pseudo-isochronous cell switching. The proposed scheme consists of two level frame hierarchy, upper and lower frame, which is used to assign the bandwidth and to guarantee the requested delay bound, respectively. Since the proposed algorithm employs two level frame hierarchy, it can overcome the coupling problem which is inherent to the framing strategy. The proposed scheme consists of two components, traffic controller and scheduller, as the imput traffic description model and regulates the input traffic specification. The function of the traffic controller is to shape real-time traffic to have the same input pattern at every switch along the path. The end-to-end delay is bounded by the scheduller which can limit the delay variation without using per-session jitter controllers, and therefore it can decrease the required buffer size. The proposed algorithm can support the QoS's of non-real time traffic as well as those of real time traffic
Implementation of a Grant Processor for Upstream Cell Transmission at the ONU in the ATM-PON
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 5C, 2002, Pages 454~464
In the ATM-PON (Asynchronous Transfer Mode-Passive Optical Network), the downstream cell transmitted by an OLT is broadcast to all ONUs. The ONU receives selectively its own cells by VP filtering. On the other hand, the upstream cell can be transmitted by ONU in the case of receiving a grant from the OLT. After providing the grant to an ONU, the OLT expects the arrival of a cell after an elapse of the equalized round trip delay. ITU-T G.983.1 recommends that one bit error is allowed between the expected arrival time and the actual arrival time at the OLT. Because the ONU processes the different delay to each type of grant (ranging, user cell, and mimi-slot grant), it is not simple to design the transmission part of ONU. In this paper, we implement a grant processor which provides the delay accurately in the ONU TC chip with the FPGA. For the given equalized delay, it deals with the delay for the cell, the byte, and the bit unit by using the shift register, the byte counter, and the D flip-flop, respectively. We verify the operation of the grant processor by the time simulation and the measurement of the optical board output.
Design of Statistical-QoS VPN in IP Networks
Lee, Hoon ; Uh, Yoon ;
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 5C, 2002, Pages 465~473
In this paper the authors propose a theoretic framework to design the Virtual Private Network (VPN) via which the Quality of Services (QoSs) are guaranteed over IP networks. The required QoS is a very strict packet loss probability or a probability that packet delay does not exceed a certain target value in a statistical manner. QoSs are guaranteed by providing a statistical bandwidth similar to equivalent bandwidth, which is computed so that the provided bandwidth is sufficient to guarantee those requirements. Two typical network architectures are considered in constructing VPN, the customer pipe scheme and the Hose scheme, and we propose a method to compute the amount of the required bandwidth for the two schemes. Finally, we investigate the implication of the scheme via numerical experiments.
Buffer Management Mechanism Using DT-DFBA Algorithm for GFR Service
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 5C, 2002, Pages 474~485
To keep simplicity that needs for GFR service and improve fairness of FIFO based buffer management algorithm, we propose a new LBO threshold decision mechanism. Proposed mechanism uses dynamic threshold that are adjusted according to the sum of active VC's weight. We reformed DT-DFBA(Differential Threshold-Differential Fair Buffer Allocation) algorithm using proposed LBO threshold decision mechanism with existing DFBA algorithm.
HFIFO(Hierarchical First-In First-Out) : A Delay Reduction Method for Frame-based Packet Transmit Scheduling Algorithm
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 5C, 2002, Pages 486~495
In this paper, we propose a delay reduction method for frame-based packet transmit scheduling algorithm. A high-speed network such as ATM network has to provide some performance guarantees such as bandwidth and delay bound. Framing strategy naturally guarantees bandwidth and enables simple rate-control while having the inherently bad delay characteristics. The proposed delay reduction method uses the same hierarchical frame structure as HRR (Hierarchical Round-Robin) but does not use the static priority scheme such as round-robin. Instead, we use a dynamic priority change scheme so that the delay unfairness between wide bandwidth connection and narrow bandwidth connection can be eliminated. That is, we use FIFO (First-In First-Out) concept to effectively reduce the occurrence of worst-case delay and to enhance delay distribution. We compare the performance for the proposed algorithm with that of HRR. The analytic and simulation results show that HFIFO inherits almost all merits of HRR with fairly better delay characteristics.
Design of Phase Shift Lines in Linear Power Amplifier Using Shifted Photonic Bandgap
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 5C, 2002, Pages 496~499
In this paper, a phase shifter with shifting photonic bandgap(PBG) cell in linear feedforward amplifier is designed and fabricated in 5GHz wireless LAN band. Now a day, the phase shifter has been fabricated with hybrid type. In this paper, a portion of PBG cell is shifted for the tuning phase. The phase shift was achieved maximum 80o in our PBG structure. Shifting PBG cell has been applied in feedforward main loop to cancel the main two tone signal.
Design of Frequency Synthesizer using Novel Architecture Programmable Frequency Divider
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 5C, 2002, Pages 500~505
In this paper, a novel architecture of programmable divider with fifty percent duty cycle output and programmable dividing number has been proposed. Through HSPICE simulation, a 900MHz frequency synthesizer with proposed frequency divider has designed in a standard 0.25
CMOS technology. To verify the operation of proposed frequency divider, a chip had been fabricated using 0.65
2-poly, 3-metal standard CMOS processing and experimental result shows that the proposed frequency divider works well. The designed voltage controlled oscillator(VCO) has a center frequency of 900MHz, a tuning range of
10%, and a gain of 154MHz/V. The simulated frequency synthesizer performance has a settling time of 1.5
, a frequency range from 820MHz to 1GHz and power consumption of 70mW at 2.5V power supply voltage.
A Novel Waveguide-based Ka-band Power Divider/Combiner Using Slotline-to-Microstrip Transitions
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 5C, 2002, Pages 506~511
In this paper, waveguide-based power combiner using conventional slotline-to-microstrip transition was proposed at Ka-band. The proposed 2-way and 4-way power combiner consist of waveguide-to-slotline transition, two or four slotline-to-microstrip transitions, and impedance matching networks. Their structures were simulated and optimized by 3-D FEM simulation. The 2-way power combiner showed a very low back-to-back insertion loss of 1.0 dB and return loss better than 15 dB from 25.7 GHz to 29.8 GHz except the resonant frequency. The 2-way power combining approach was extended to 4-way power combining using slotline tee junction. The 4-way power combiner showed the similar performance to that of 2-way power combiner with 2 GHz smaller bandwidth.
An Optimal Instruction Fetch Strategy for SMT Processors
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 5C, 2002, Pages 512~521
Recently, conventional superscalar RISC processors arrive their performance limit, and many researches on the next-generation architecture are concentrated on SMT(Simultaneous Multi-Threading). In SMT processors, multiple threads are executed simultaneously and share hardware resources dynamically. In this case, it is more important to supply instructions from multiple threads to processor core efficiently than ever. Because SMT architecture shows higher IPC(Instructions per cycle) than superscalar architecture, performance is influenced by fetch bandwidth and the size of fetch queue. Moreover, to use TLP(Thread Level Parallelism) efficiently, fetch thread selection algorithm and fetch bandwidth for each selected threads must be carefully designed. Thus, in this paper, the performance values influenced by these factors are analyzed. Based on the results, an optimal instruction fetch strategy for SMT processors is proposed.
High performance V-Band Downconverter Module
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 5C, 2002, Pages 522~529
MMIC circuits in whole receiver system was fabricated based on GaAs pHEMT technology. And a V-band downconverter module was fabricated by integrating these circuits. The downconverter module consists of a LO drive power amplifier which generates 24dBm output power, a low noise amplifier(LNA) which shows 20 dB small signal gain, an active parallel feedback oscillator which generates 1.6 dBm output power, and a cascode mixer which shows over 6dB conversion gain. The good conversion gain performance of our mixer made no need to attach any IF amplifier which grows conversion gain. Measured results of the complete downconverter show a conversion gain of over 20 dB between 57.5 GHz and 61.7GHz without IF amplifier.
A Study on the new structure Voltage Controlled Hair-pin Resonator Oscillator using parallel feedback of second-harmonic
The Journal of Korean Institute of Communications and Information Sciences, volume 27, issue 5C, 2002, Pages 530~534
In the thesis, For improving the Stability of VCHRO(Voltage Controlled Hair-pin Resonator Oscillator) the new structure using the parallel feedback of the second harmonic is proposed for self-phase locking effect. This module is composed of wilkinson divider, frequency doubler, directional coupler, and bandpass filter using a hair-pin resonator, which are integrated into miniaturized hybrid circuit. The module exhibits output power of 2.5 dBm at 19.5 GHz, -29.83 dBc fundamental frequency suppression and -76.52 dBc/Hz phase noise at 10 kHz offset frequency from carrier of center frequency 19.5 GHz.