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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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The Journal of Korean Institute of Communications and Information Sciences
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The Korean Institute of Communications and Information Sciences
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Volume & Issues
Volume 29, Issue 12C - Dec 2004
Volume 29, Issue 12B - Dec 2004
Volume 29, Issue 12A - Dec 2004
Volume 29, Issue 11C - Nov 2004
Volume 29, Issue 11B - Nov 2004
Volume 29, Issue 11A - Nov 2004
Volume 29, Issue 10C - Oct 2004
Volume 29, Issue 10B - Oct 2004
Volume 29, Issue 10A - Oct 2004
Volume 29, Issue 9C - Sep 2004
Volume 29, Issue 9B - Sep 2004
Volume 29, Issue 9A - Sep 2004
Volume 29, Issue 8C - Aug 2004
Volume 29, Issue 8B - Aug 2004
Volume 29, Issue 8A - Aug 2004
Volume 29, Issue 7C - Jul 2004
Volume 29, Issue 7B - Jul 2004
Volume 29, Issue 7A - Jul 2004
Volume 29, Issue 6C - Jun 2004
Volume 29, Issue 6B - Jun 2004
Volume 29, Issue 6A - Jun 2004
Volume 29, Issue 5C - May 2004
Volume 29, Issue 5B - May 2004
Volume 29, Issue 5A - May 2004
Volume 29, Issue 4C - Apr 2004
Volume 29, Issue 4B - Apr 2004
Volume 29, Issue 4A - Apr 2004
Volume 29, Issue 3C - Mar 2004
Volume 29, Issue 3B - Mar 2004
Volume 29, Issue 3A - Mar 2004
Volume 29, Issue 2C - Feb 2004
Volume 29, Issue 2B - Feb 2004
Volume 29, Issue 2A - Feb 2004
Volume 29, Issue 1C - Jan 2004
Volume 29, Issue 1B - Jan 2004
Volume 29, Issue 1A - Jan 2004
Selecting the target year
A novel gain-clamping technique for EDFA in WDM add/drop networks
The Journal of Korean Institute of Communications and Information Sciences, volume 29, issue 4A, 2004, Pages 363~369
We propose, for the first time to our knowledge, a novel gain-clamping method for EDFA in WDM add/drop networks by introducing a disturbance observer technique. The control input signal for gain-clamping is composed of a nominal control signal and an additional control signal of compensating the gain fluctuations caused by channel add/drops. Based on disturbance observer technique, we designed the additional control signal such that it has the compensating information of estimated disturbance resulted from channel add/drops. The circuit for generating additional control signal can easily be implemented by using simple electronic devices. We proved the superiority of the new technique over the previous ones by showing simulation results of minimized dips and spikes that appear in power profile of EDFA in the process of channel add/drops.
Adaptive OFDM with Channel Predictor in Broadband Wireless Mobile Communications
The Journal of Korean Institute of Communications and Information Sciences, volume 29, issue 4A, 2004, Pages 370~377
In this paper, we present an adaptive modulation technique for orthogonal frequency division multiplexing (OFDM) for broadband wireless communications. Also, using improved channel prediction, we enhance the performance of adaptive OFDM in high mobility environments. Adaptive modulation technique has been shown to achieve reliable high-rate data transmission over frequency-selective fading channel when OFDM is employed. This scheme requires the accurate channel information between two stations for a better performance. In an outdoor high mobility environment, most of adaptive OFDM systems have to be given the channel information transmitted from the receiver. Even if it is possible, there is some delay. Moreover, the channel impulse response between two stations is very rapidly varied. If the channel information is obsolete at the time of transmission, then poor system performance will result. In order to solve this problem, we propose adaptive OFDM with improved channel predictor. The proposed bit allocation algorithm has a lower complexity and the proposed scheme mitigates the effect of channel delay. Robust approach is less sensitive to outdated channel information. Performance results show that the proposed scheme can achieve considerable performance enhancement.
Improved OFDM System with Carrier Interferometry Codes in Highly Dispersive Fading Channels
Chung, Yeon-Ho ;
The Journal of Korean Institute of Communications and Information Sciences, volume 29, issue 4A, 2004, Pages 378~383
Orthogonal Frequency Division Multiplexing (OFDM) transmits high-speed data by splitting the transmission bandwidth into a number of subcarriers. The bandwidth of each subcarrier is ensured to be smaller than the coherence bandwidth. This paper presents an OFDM system incorporated with the Carrier Interferometry (CI) codes to improve the performance by enhancing frequency diversity effect. The performances of CI-OFDM with multilevel modulations are investigated in highly dispersive fading channels. For the investigation of performance improvement of CI-OFDM, a simulator has been developed using a well-known SPW simulation platform. The simulation results show that the CI-OFDM provides both performance improvement and robustness against dispersive fading channel behavior. The performance of CI-OFBM with multilevel modulations demonstrates that CI-OFDM outperforms a traditional OFDM system, particularly in highly dispersive channels. With a relatively large delay spread of 151㎱ compared to the guard interval of 800㎱, CI-OFDM provides a BER of 10
if sufficient signal power is present.
Efficient Channel Estimator based on Channel Correlation in a Mobile MIMO OFDM System
The Journal of Korean Institute of Communications and Information Sciences, volume 29, issue 4A, 2004, Pages 384~389
In this paper, we investigate channel estimation techniques based on the comb-type pilot arrangement for a mobile MIMO OFDM system. Moreover, to enhance channel estimation, an efficient channel estimation technique is proposed. Simulation results show that the proposed channel estimator is accurate and effective for tracking variations of channels between multiple transmit antennas and receive antennas in time-varying radio channels.
A Study on Automatic Interface Generation for Communication between AMBA Bus and IPs
The Journal of Korean Institute of Communications and Information Sciences, volume 29, issue 4A, 2004, Pages 390~398
This paper describes a study on the automatic generation system of the interface for communication among AMBA bus and IPs with different protocols. Employing an extended STG, the proposed system generates the interface modules required for the communication among IPs with different protocols. For an example system, the interface module for communication between AMBA AHB bus and a video decoder has been generated and verified in its functionality. The area and latency have been compared with the manually designed interface. For burst-mode communication, the generated interface module shows the comparable performance with the manually designed module. For single-mode communication, the generated interface module shows a slightly worse performance than the manually designed module. However, the increased area is negligible considering the size of the IP.
An Evolution of Software Reliability in a Large Scale Switching System: using the software
Lee, Jae-Ki ; Nam, Sang-Sik ; Kim, Chang-Bong ;
The Journal of Korean Institute of Communications and Information Sciences, volume 29, issue 4A, 2004, Pages 399~414
In this paper, an evolution of software reliability engineering in a large-scale software project is summarized. The considered software consists of many components, called functional blocks in software of switching system. These functional blocks are served as the unit of coding and test, and the software is continuously updated by adding new functional blocks. We are mainly concerned with the analysis of the effects of these software components in software reliability and reliability evolution. We analyze the static characteristics of the software related to software reliability using collected failure data during system test. We also discussed a pattern which represents a local and global growth of the software reliability as version evolves. To find the pattern of system software, we apply the S-shaped model to a collection of failure data sets of each evolutionary version and the Goel-Okumoto(G-O) model to a grouped overall failure data set. We expect this pattern analysis will be helpful to plan and manage necessary human/resources fur a new similar software project which is developed under the same developing circumstances by estimating the total software failures with respect to its size and time.
A 5.8GHz SiGe Down-Conversion Mixer with On-Chip Active Batons for DSRC Receiver
The Journal of Korean Institute of Communications and Information Sciences, volume 29, issue 4A, 2004, Pages 415~422
DSRC provides high speed radio link between Road Side Equipment and On-Board Equipment within the narrow communication area. In this paper, a 5.8 GHz down-conversion mixer for DSRC communication system was designed and fabricated using 0.8
SiGe HBT process technology and RF/LO matching circuits, RF/LO input balun circuits, and If output balun circuit were all integrated on chip. The chip size of fabricated mixer was 1.9 mm
1.3 mm and the measured performance was 7.5 ㏈ conversion gain, －2.5 ㏈m input IP3, 46 ㏈ LO to RF isolation, 56 ㏈ LO to IF isolation, current consumption of 21 mA for 3.0 V supply voltage.
Performance Improvement of WCDMA Downlink Systems Using Space Time Block Coding
The Journal of Korean Institute of Communications and Information Sciences, volume 29, issue 4A, 2004, Pages 423~428
High-data rate and high speed communication techniques are required for wireless mobile communication systems to provide multimedia services. A multiple antenna technology may be used to meet this demand. In this paper, a method for performance improvement of a WCDMA downlink system using space time block coding is proposed in quasi-static Rayleigh fading channels. The proposed receiver uses the cross correlation matrix obtained by each finger corresponding to multi paths. To obtain maximum diversity gain, the inverse of cross correlation matrix and the Hermitian matrix of the channel matrix for each path arc computed, and then applied to received signals. Various simulation results show that the proposed receiver outperforms a conventional receiver in Rayleigh fading channels.
Design and Performance Analysis of a Decision-feedback Coherent Code Tracking Loop for WCDMA Systems
The Journal of Korean Institute of Communications and Information Sciences, volume 29, issue 4A, 2004, Pages 429~438
In this paper, a decision-feedback coherent code tracking loop is designed for WCDMA systems and its performance is analyzed in terms of jitter variance considering the effect of phase and symbol estimation errors for both AWGN and fading environments. An analytical closed-form formula for jitter variance is Int derived for AWGN environments as a function of a pulse-shaping filter, timing offset, signal-to-interference ratio, and loop bandwidth while involving the phase estimation error and bit error rate, and the upper bound of jitter variance is derived for fading environments. Finally a second-order coherent code tracking loop is designed with the DPCH frame format #13 of the WCDHA forward link selected as a target system, and its performance is evaluated by the closed-form formula and compared with the simulation results for both AWGN and Rayleigh fading environments.
A High-speed St Low power Design Technique for Open Loop 2-step ADC
The Journal of Korean Institute of Communications and Information Sciences, volume 29, issue 4A, 2004, Pages 439~446
This paper describes high speed and low power design techniques for an 8-bit 500MSamples/s CMOS 2-step ADC. Instead of the conventional closed-loop architecture, the newly proposed ADC adopts open-loop architecture and uses a reset-switch to reduce loading time in an environment of big parasitic-capacitances of mux-array. An analog-latch is also used to reduce power consumption. Simulation result shows that the ADC has the SNDR of 46.91㏈ with a input frequency of 103MHz at 500Msample/s and consumes 203㎽ with a 1.8V single power supply. The chip is designed with a 0.18mm 1-poly 6-metal CMOS technology and occupies active area of 760
Design of an Optimal RSA Crypto-processor for Embedded Systems
The Journal of Korean Institute of Communications and Information Sciences, volume 29, issue 4A, 2004, Pages 447~457
This paper proposes a RSA crypto-processor for embedded systems. The architecture of the RSA crypto-processor should be used relying on Big Montgomery algorithm, and is supported by configurable bit size. The RSA crypto-processor includes a RSA control signal generator, an optimal Big Montgomery processor(adder, multiplier). We use diverse arithmetic unit (adder, multiplier) algorithm. After we compared the various results, we selected the optimal arithmetic unit which can be connected with ARM core-processor. The RSA crypto-processor was implemented with Verilog HDL with top-down methodology, and it was verified by C language and Cadence Verilog-XL. The verified models were synthesized with a Hynix 0.25
, CMOS standard cell library while using Synopsys Design Compiler. The RSA crypto-processor can operate at a clock speed of 51 MHz in this worst case conditions of 2.7V, 10
and has about 36,639 gates.
A design of the linearly controlled CMOS Attenuator
The Journal of Korean Institute of Communications and Information Sciences, volume 29, issue 4A, 2004, Pages 458~465
To reaffirm the use of a mainstream CMOS process for designing passive-like attenuator structures, a linearly controlled variable attenuator is realized with 0.35
2-poly 4-metal CMOS process. It uses the П configuration for large attenuation range and suitable matching property. Compared to conventional passive-like CMOS attenuators, it is demonstrated that this work advances the frequency band from MHz to ㎓ (DC- l㎓), and reduces the size to 700
.. Both simulation results and test results are provided. They show the improved linear relation between attenuation and control voltage. It is very useful in CDMA or GSM band, which uses under 1㎓ frequency band. An alternative topology, Bridged-T configuration, is proposed to get over the limit of applications by elevating operation bandwidth. The proposed topology covers over DC-2㎓ frequency band, which means that the proposed architecture can cover the tripleband (800MHz CDMA/GSM, 1.5㎓ GPS, 1.9㎓z PCS system) in applications as well. The simulation results are provided.
A Circuit Design of Fingerprint Authentication Sensor
The Journal of Korean Institute of Communications and Information Sciences, volume 29, issue 4A, 2004, Pages 466~471
This paper proposes an advanced circuit for fingerprint sensor signal processing. We increased the voltage between ridge and valley by modifying the parasitic capacitance eliminating circuit of sensor plate. The analog comparator was designed for comparing the sensor signal voltage with the reference signal voltage. 1-Pixel Fingerprint sensor circuit was designed and simulated, and the layout was performed.