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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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Journal DOI :
Electronics and Telecommunications Research Institute
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Volume & Issues
Volume 19, Issue 4 - Dec 1997
Volume 19, Issue 3 - Oct 1997
Volume 19, Issue 2 - Jul 1997
Volume 19, Issue 1 - Apr 1997
Volume 18, Issue 4 - Jan 1997
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High-Speed Array Multipliers Based on On-the-Fly Conversion
Moh, Sang-Man ; Yoon, Suk-Han ;
ETRI Journal, volume 19, issue 4, 1997, Pages 317~317
A new on-the-fly conversion algorithm is proposed, and high-speed array multipliers with the on-the-fly conversion are presented. The new on-the-fly conversion logic is used to speed up carry-propagate addition at the last stage of multiplication, and provides constant delay independent of the number of input bits. In this paper, the multiplication architecture and the on-the-fly conversion algorithm are presented and discussed in detail. The proposed architecture has multiplication time of (n +1)
, Where n is the number of input bits and
is the delay of a full adder. According to our comparative performance evaluation, the proposed architecture has shorter delay and requires less area than the conventional array multiplier with on-the-fly conversion.
Discrete-Time Queuing Analysis of Dual-Plane ATM Switch with Synchronous Connection Control
Choi, Jun-Kyun ;
ETRI Journal, volume 19, issue 4, 1997, Pages 326~326
In this paper, we propose an ATM switch with the rate more than gigabits per second to cope with future broadband service environments. The basic idea is to separate the connection control flow from the data information flow inside the switch. The proposed switch has a dual-plane switch matrix with the synchronous control algorithm. The queuing behaviors of the proposed switch are shown by the discrete-time queuing analysis. Numerical analyses are taken both in the non-blocking crossbar switch and the banyan switch with internal blocking. Results show that a proposed dual-plane
switch would have the acceptable performance with maximum throughput of about 95 percent.
An Experimental Delay Analysis Based on M/G/1-Vacation Queues for Local Audio/Video Streams
Kim, Doo-Hyun ; Lee, Kyung-Hee ; Kung, Sang-Hwan ; Kim, Jin-Hyung ;
ETRI Journal, volume 19, issue 4, 1997, Pages 344~344
The delay which is one of the quality of service parameters is considered to be a crucial factor for the effective usage of real-time audio and video streams in interactive multimedia collaborations. Among the various causes of the delay, we focus in this paper on the local delay concerned with the schemes which handle continuous inflow of encoded data from constant or variable bit-rate audio and video encoders. We introduce two kinds of implementation approaches, pull model and push model. While the pull model periodically pumps out the incoming data from the system buffer, the push model receives events from the device drivers. From our experiments based on Windows NT 3.51, it is shown that the push model outperforms the other for both constant and variable bit-rate streams in terms of the local delay, when the system suffers reasonable loads. We interpret this experimental data with M/G/1 multiple vacation queuing theories, and show that it is consistent with the queuing theoretic interpretations.
Automated Test Generation from Specifications Based on Formal Description Techniques
Chin, Byoung-Moon ; Choe, Young-Han ; Kim, Sung-Un ; Jung, Jae-Il ;
ETRI Journal, volume 19, issue 4, 1997, Pages 363~363
This paper describes a research result on automatic generation of abstract test cases from formal specifications by applying many related algorithms and techniques such as the testing framework, rural Chinese postman tour and unique input output sequence concepts. In addition, an efficient algorithm for verifying the strong connectivity of the reference finite state machine and the concept of unique event sequence are explained. We made use of several techniques to from an integrated framework for abstract test case generation from LOTOS and SDL specifications. A prototype of the proposed framework has been built with special attention to real protocol in order to generate the executable test cases in an automatic way. The abstract test cases in tree and tabular combined notation (TTCN) language will be applied to the TTCN compiler in order to obtain the executable test cases which re relevant to the industrial application.
Correlation Immune Functions with Controllable Nonlinearity
Chee, Seong-Taek ; Lee, Sang-Jin ; Kim, Kwang-Jo ; Kim, Dae-Ho ;
ETRI Journal, volume 19, issue 4, 1997, Pages 389~389
In this paper, we consider the relationship between nonlinearity and correlation immunity of Boolean functions. In particular, we discuss the nonlinearity of correlation immune functions suggested by P. Camion et al. For the analysis of such functions, we present a simple method of generating the same set of functions, which makes it possible to construct correlation immune functions with controllable correlation immunity and nonlinearity. Also, we find a bound for the correlation immunity of functions having maximal nonlinearity.
An Amorphous Silicon Local Interconnection (ASLI) CMOS with Self-Aligned Source/Drain and Its Electrical Characteristics
Yoon, Yong-Sun ; Baek, Kyu-Ha ; Park, Jong-Moon ; Nam, Kee-Soo ;
ETRI Journal, volume 19, issue 4, 1997, Pages 402~402
A CMOS device which has an extended heavily-doped amorphous silicon source/drain layer on the field oxide and an amorphous silicon local interconnection (ASLI) layer in the self-aligned source/drain region has been studied. The ASLI layer has some important roles of the local interconnections from the extended source/drain to the bulk source/drain and the path of the dopant diffusion sources to the bulk. The junction depth and the area of the source/drain can be controlled easily by the ASLI layer thickness. The device in this paper not only has very small area of source/drain junctions, but has very shallow junction depths than those of the conventional CMOS device. An operating speed, however, is enhanced significantly compared with the conventional ones, because the junction capacitance of the source/drain is reduced remarkably due to the very small area of source/drain junctions. For a 71-stage unloaded CMOS ring oscillator, 128 ps/gate has been obtained at power supply voltage of 3.3V. Utilizing this proposed structure, a buried channel PMOS device for the deep submicron regime, known to be difficult to implement, can be fabricated easily.