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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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Journal DOI :
Electronics and Telecommunications Research Institute
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Volume & Issues
Volume 25, Issue 6 - Dec 2003
Volume 25, Issue 5 - Oct 2003
Volume 25, Issue 4 - Aug 2003
Volume 25, Issue 3 - Jun 2003
Volume 25, Issue 2 - Apr 2003
Volume 25, Issue 1 - Feb 2003
Selecting the target year
Dual Cache Architecture for Low Cost and High Performance
Lee, Jung-Hoon ; Park, Gi-Ho ; Kim, Shin-Dug ;
ETRI Journal, volume 25, issue 5, 2003, Pages 275~275
We present a high performance cache structure with a hardware prefetching mechanism that enhances exploitation of spatial and temporal locality. Temporal locality is exploited by selectively moving small blocks into the direct-mapped cache after monitoring their activity in the spatial buffer. Spatial locality is enhanced by intelligently prefetching a neighboring block when a spatial buffer hit occurs. We show that the prefetch operation is highly accurate: over 90% of all prefetches generated are for blocks that are subsequently accessed. Our results show that the system enables the cache size to be reduced by a factor of four to eight relative to a conventional direct-mapped cache while maintaining similar performance.
Low Power 260k Color TFT LCD Driver IC
Kim, Bo-Sung ; Ko, Jae-Su ; Lee, Won-Hyo ; Park, Kyoung-Won ; Hong, Soon-Yang ;
ETRI Journal, volume 25, issue 5, 2003, Pages 288~288
In this study, we present a 260k color TFT LCD driver chip set that consumes only 5 mW in the module, which has exceptionally low power consumption. To reduce power consumption, we used many power-lowering schemes in the logic and analog design. A driver IC for LCDs has a built-in graphic SRAM. Besides write and read operations, the graphic SRAM has a scan operation that is similar to the read operation of one row-line, which is displayed on one line in an LCD panel. Currently, the embedded graphic memory is implemented by an 8-transistor leaf cell and a 6-transistor leaf cell. We propose an efficient scan method for a 6-transistor embedded graphic memory that is greatly improved over previous methods. The proposed method is implemented in a 0.22
process. We demonstrate the efficacy of the proposed method by measuring and comparing the current consumption of chips with and without our proposed scheme.
Pipelined Macroblock Processing to Reduce Internal Buffer Size of Motion Estimation in Multimedia SoCs
Lee, Seong-Soo ;
ETRI Journal, volume 25, issue 5, 2003, Pages 297~297
A multimedia SoC often requires a large internal buffer, because it must store the whole search window to reduce the huge I/O bandwidth of motion estimation. However, the silicon area of the internal buffer increases tremendously as the search range becomes larger. This paper proposes a new method that greatly reduces the internal buffer size of a multimedia SoC while the computational cost, I/O bandwidth, and image quality do not change. In the proposed method, only the overlapped parts of search windows for consecutive macroblocks are stored in the internal buffer. The proposed method reduces the internal buffer. The proposed method reduces the internal buffer size to 1/5.0 and 1/8.8 when the search range is
Soft IP Compiler for a Reed-Solomon Decoder
Park, Jong-Kang ; Kim, Jong-Tae ;
ETRI Journal, volume 25, issue 5, 2003, Pages 305~305
In this paper, we present a soft IP compiler for the Reed-Solomon decoder that generates a fully synthesizable VHDL core exploiting characteristic parameters and design constraints that we newly classify for the soft IP. It produces a structural design with an estimable regular architecture based on a finite state machine with a datapath (FSMD). Since characteristic parameters provide different design points on the design space, using one of two simple procedures called the constructive search with area increment (CSAI) and constructive search with speed decrement (CSSD) for design space exploration, the core compiler makes it possible for an IP user to create the Reed-Solomon decoder with appropriate sub-architectures without synthesizing many models. Experimental results show that the IP compiler can apply to several industry standards.
A Scalable Structure for a Multiplier and an Inversion Unit in
Lee, Chan-Ho ; Lee, Jeong-Ho ;
ETRI Journal, volume 25, issue 5, 2003, Pages 315~315
Elliptic curve cryptography (ECC) offers the highest security per bit among the known public key cryptosystems. The operation of ECC is based on the arithmetic of the finite field. This paper presents the design of a 193-bit finite field multiplier and an inversion unit based on a normal basis representation in which the inversion and the square operation units are easy to implement. This scalable multiplier can be constructed in a variable structure depending on the performance area trade-off. We implement it using Verilog HDL and a 0.35
CMOS cell library and verify the operation by simulation.
Efficient Test Data Compression and Low Power Scan Testing in SoCs
Jung, Jun-Mo ; Chong, Jong-Wha ;
ETRI Journal, volume 25, issue 5, 2003, Pages 321~321
Testing time and power consumption during the testing of SoCs are becoming increasingly important with an increasing volume of test data in intellectual property cores in SoCs. This paper presents a new algorithm to reduce the scan-in power and test data volume using a modified scan latch reordering algorithm. We apply a scan latch reordering technique to minimize the column hamming distance in scan vectors. During scan latch reordering, the don't-care inputs in the scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.
A Fully Synthesizable Bluetooth Baseband Module for a System-on-a-Chip
Chun, Ik-Jae ; Kim, Bo-Gwan ; Park, In-Cheol ;
ETRI Journal, volume 25, issue 5, 2003, Pages 328~328
Bluetooth is a specification for short-range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area-efficient digital baseband module for wireless technology. For area-efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware-efficient functions, such as low-level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB)interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core no system-on-a-chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a
CMOS technology, the core size of which was only 2.79
AE32000B: a Fully Synthesizable 32-Bit Embedded Microprocessor Core
Kim, Hyun-Gyu ; Jung, Dae-Young ; Jung, Hyun-Sup ; Choi, Young-Min ; Han, Jung-Su ; Min, Byung-Gueon ; Oh, Hyeong-Cheol ;
ETRI Journal, volume 25, issue 5, 2003, Pages 337~337
In this paper, we introduce a fully synthesizable 32-bit embedded microprocessor core called the AE32000B. The AE32000B core is based on the extendable instruction set computer architecture, so it has high code density and a low memory access rate. In order to improve the performance of the core, we developed and adopted various design options, including the load extension register instruction (LERI) folding unit, a high performance multiply and accumulate (MAC) unit, various DSP units, and an efficient coprocessor interface. The instructions per cycle count of the Dhrystone 2.1 benchmark for the designed core is about 0.86. We verified the synthesizability and the area and time performances of our design using two CMOS standard cell libraries: a 0.35-
library and a 0.18-
library. With the 0.35-
library, the core can be synthesized with about 47,000 gates and operate at 70 MHz or higher, while it can be synthesized with about 53,000 gates and operate at 120 MHz or higher with the 0.18-
Design of M-Channel IIR Uniform DFT Filter Banks Using Recursive Digital Filters
Dehghani, M.J. ; Aravind, R. ; Prabhu, K.M.M. ;
ETRI Journal, volume 25, issue 5, 2003, Pages 345~345
In this paper, we propose a method for designing a class of M-channel, causal, stable, perfect reconstruction, infinite impulse response (IIR), and parallel uniform discrete Fourier transform (DFT) filter banks. It is based on a previously proposed structure by Martinez et al.  for IIR digital filter design for sampling rate reduction. The proposed filter bank has a modular structure and is therefore very well suited for VLSI implementation. Moreover, the current structure is more efficient in terms of computational complexity than the most general IIR DFT filter bank, and this results in a reduced computational complexity by more than 50% in both the critically sampled and oversampled cases. In the polyphase oversampled DFT filter bank case, we get flexible stop-band attenuation, which is also taken care of in the proposed algorithm.
A Dynamic Packet Recovery Mechanism for Realtime Service in Mobile Computing Environments
Park, Kwang-Roh ; Oh, Yeun-Joo ; Lim, Kyung-Shik ; Cho, Kyoung-Rok ;
ETRI Journal, volume 25, issue 5, 2003, Pages 356~356
This paper analyzes the characteristics of packet losses in mobile computing environments based on the Gilbert model and then describes a mechanism that can recover the lost audio packets using redundant data. Using information periodically reported by a receiver, the sender dynamically adjusts the amount and offset values of redundant data with the constraint of minimizing the bandwidth consumption of wireless links. Since mobile computing environments can be often characterized by frequent and consecutive packet losses, loss recovery mechanism need to deal efficiently with both random and consecutive packet losses. To achieve this, the suggested mechanism uses relatively large, discontinuous exponential offset values. That gives the same effect as using both the sequential and interleaving redundant information. To verify the effectiveness of the mechanism, we extended and implemented RTP/RTCP and applications. The experimental results show that our mechanism, with an exponential offset, achieves a remarkably low complete packet loss rate and adapts dynamically to the fluctuation of the packet loss pattern in mobile computing environments.
An Efficient Handover Mechanism Using the General Switch Management Protocol on a Multi-Protocol Label Switching Network
Choi, Seong-Gon ; Kang, Hyun-Joo ; Choi, Jun-Kyun ;
ETRI Journal, volume 25, issue 5, 2003, Pages 369~369
Using the general switch management protocol on a multi-protocol label switching network, we present an efficient method for handling handovers. The proposed method directly changes an established path into a new path for supporting a handover. Our investigation reveals the effects of the proposed scheme and demonstrates that this method significantly reduces signaling costs and delays.
A Dual-Mode Narrow-Band Channel Filter and Group-Delay Equalizer for a Ka-Band Satellite Transponder
Kahng, Sung-Tek ; Uhm, Man-Seok ; Lee, Seong-Pal ;
ETRI Journal, volume 25, issue 5, 2003, Pages 379~379
This paper presents the design of a narrow-band channel filter and its group-delay equalizer for a Ka-band satellite transponder. We used an 8th order channel filter for high selectivity with an elliptic-integral function response and an inline configuration. We designed a 2-pole, reflection-type, group-delay equalizer to compensate for the steep variation of the group-delay at the output of the channel filter, keeping the thermal stability at
ns of group-delay variation at the band edges over 15-55
. We devised a new tuning technique using short-ended dummy cavities and used it for tuning both the filter and equalizer; this removes the necessity of additional tuning after the cavities are assembled. Through measurement, we demonstrate that the group-delay-equalized filter meets the equipment requirements and is appropriate for satellite input multiplexers.
Operational Report of the Mission Analysis and Planning System for the KOMPSAT-I
Lee, Byoung-Sun ; Lee, Jeong-Sook ; Kim, Jae-Hoon ; Lee, Seong-Pal ; Kim, Hae-Dong ; Kim, Eun-Kyou ; Choi, Hae-Jin ;
ETRI Journal, volume 25, issue 5, 2003, Pages 387~387
Since its launching on 21 December 1999, the Korea Multi-Purpose Satellite-I (KOMPSAT-I) has been successfully operated by the Mission Control Element (MCE), which was developed by the ETRI. Most of the major functions of the MCE have been successfully demonstrated and verified during the three years of the mission life of the satellite. This paper presents the operational performances of the various functions in MAPS. We show the performance and analysis of orbit determinations using ground-based tracking data and GPS navigation solutions. We present four instances of the orbit maneuvers that guided the spacecraft form injection orbit into the nominal on-orbit. We include the ground-based attitude determination using telemetry data and the attitude maneuvers for imaging mission. The event prediction, mission scheduling, and command planning functions in MAPS subsequently generate the spacecraft mission operations and command plan. The fuel accounting and the realtime ground track display also support the spacecraft mission operations.
A New Similarity Measure Based on Intraclass Statistics for Biometric Systems
Lee, Kwan-Yong ; Park, Hye-Young ;
ETRI Journal, volume 25, issue 5, 2003, Pages 401~401
A biometric system determines the identity of a person by measuring physical features that can distinguish that person from others. Since biometric features have many variations and can be easily corrupted by noises and deformations, it is necessary to apply machine learning techniques to treat the data. When applying the conventional machine learning methods in designing a specific biometric system, however, one first runs into the difficulty of collecting sufficient data for each person to be registered to the system. In addition, there can be an almost infinite number of variations of non-registered data. Therefore, it is difficult to analyze and predict the distributional properties of real data that are essential for the system to deal with in practical applications. These difficulties require a new framework of identification and verification that is appropriate and efficient for the specific situations of biometric systems. As a preliminary solution, this paper proposes a simple but theoretically well-defined method based on a statistical test theory. Our computational experiments on real-world data show that the proposed method has potential for coping with the actual difficulties in biometrics.
A High-Gain Microstrip Patch Array Antenna Using a Superstrate Layer
Choi, Won-Kyu ; Cho, Yong-Heui ; Pyo, Cheol-Sik ; Choi, Jae-Ick ;
ETRI Journal, volume 25, issue 5, 2003, Pages 407~407
A dielectric superstrate layer above a microstrip patch antenna has remarkable effects on its gain and resonant characteristics. This paper experimentally investigates the effect of a superstrate layer for high gain on microstrip patch antennas. We measured the gain of antennas with and without a superstrate and found that the gain of a single patch with a superstrate was enhanced by about 4 dBi over the one without a superstrate at 12 GHz. The impedance bandwidths of a single patch with and without a superstrate for VSWR < 2 were above 11%. The designed
array antenna using a superstrate had a high gain of over 22.5 dB and a wide impedance bandwidth of over 17%.
New Iron-Containing Electrode Materials for Lithium Secondary Batteries
Hong, Young-Sik ; Ryu, Kwang-Sun ; Chang, Soon-Ho ;
ETRI Journal, volume 25, issue 5, 2003, Pages 412~412
Using a galvanostatic charge/discharge cycler and cyclic voltammetry, we investigated for the first time the electrochemical properties of iron-containing minerals, such as chalcophanite, diadochite, schwertmannite, laihuite, and tinticite, as electrode materials for lithium secondary batteries. Lithium insertion into the mineral diadochite showed a first discharge capacity of about 126 mAh/g at an average voltage of 3.0 V vs.
, accompanied by a reversible capacity of 110 mAh/g at the 60th cycle. When the cutoff potential was down to 1.25 V, the iron was further reduced, giving rise to a new plateau at 1.3 V. Although the others showed discharge plateaus at low potentials of less than 1.6 V, these results give an important clue for the development of new electrode materials.
An Unbiased Signal-to-Interference Ratio Estimator for the High Speed Downlink Packet Access System
Won, Seok-Ho ; Kim, Whan-Woo ; Ahn, Jae-Min ; Lyu, Deuk-Su ;
ETRI Journal, volume 25, issue 5, 2003, Pages 418~418
We propose an unbiased signal-to-interference ratio (SIR) estimator for the high speed downlink packet access (HSDPA) system. The proposed SIR estimator solves the problem of underestimation present in conventional SIR estimators and is suitable for channel quality measurement in the adaptive modulation and coding scheme of HSDPA, which requires accurate SIR estimation for optimum adaptive modulation and coding selection. Our analysis and simulation results demonstrate the improved estimation performance of the proposed SIR estimator.