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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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Journal DOI :
Electronics and Telecommunications Research Institute
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Volume & Issues
Volume 26, Issue 6 - Dec 2004
Volume 26, Issue 5 - Oct 2004
Volume 26, Issue 4 - Aug 2004
Volume 26, Issue 3 - Jun 2004
Volume 26, Issue 2 - Apr 2004
Volume 26, Issue 1 - Feb 2004
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A Low Power 16-Bit RISC Microprocessor Using ECRL Circuits
Shin, Young-Joon ; Lee, Chan-Ho ; Moon, Yong ;
ETRI Journal, volume 26, issue 6, 2004, Pages 513~513
This paper presents a low power 16-bit adiabatic reduced instruction set computer (RISC) microprocessor with efficient charge recovery logic (ECRL) registers. The processor consists of registers, a control block, a register file, a program counter, and an arithmetic and logical unit (ALU). Adiabatic circuits based on ECRL are designed using a
CMOS technology. An adiabatic latch based on ECRL is proposed for signal interfaces for the first time, and an efficient four-phase supply clock generator is designed to provide power for the adiabatic processor. A static CMOS processor with the same architecture is designed to compare the energy consumption of adiabatic and non-adiabatic microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is about 1/3 compared to that of the static CMOS microprocessor.
An Efficient Built-in Self-Test Algorithm for Neighborhood Pattern- and Bit-Line-Sensitive Faults in High-Density Memories
Kang, Dong-Chual ; Park, Sung-Min ; Cho, Sang-Bock ;
ETRI Journal, volume 26, issue 6, 2004, Pages 520~520
As the density of memories increases, unwanted interference between cells and the coupling noise between bit-lines become significant, requiring parallel testing. Testing high-density memories for a high degree of fault coverage requires either a relatively large number of test vectors or a significant amount of additional test circuitry. This paper proposes a new tiling method and an efficient built-in self-test (BIST) algorithm for neighborhood pattern-sensitive faults (NPSFs) and new neighborhood bit-line sensitive faults (NBLSFs). Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is utilized. This four-cell layout needs smaller test vectors, provides easier hardware implementation, and is more appropriate for both NPSFs and NBLSFs detection. A CMOS column decoder and the parallel comparator proposed by P. Mazumder are modified to implement the test procedure. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present algorithm properties such as the capability to detect stuck-at faults, transition faults, conventional pattern-sensitive faults, and neighborhood bit-line sensitive faults.
Error Concealment Based on Semantic Prioritization with Hardware-Based Face Tracking
Lee, Jae-Beom ; Park, Ju-Hyun ; Lee, Hyuk-Jae ; Lee, Woo-Chan ;
ETRI Journal, volume 26, issue 6, 2004, Pages 535~535
With video compression standards such as MPEG-4, a transmission error happens in a video-packet basis, rather than in a macroblock basis. In this context, we propose a semantic error prioritization method that determines the size of a video packet based on the importance of its contents. A video packet length is made to be short for an important area such as a facial area in order to reduce the possibility of error accumulation. To facilitate the semantic error prioritization, an efficient hardware algorithm for face tracking is proposed. The increase of hardware complexity is minimal because a motion estimation engine is efficiently re-used for face tracking. Experimental results demonstrate that the facial area is well protected with the proposed scheme.
An Area Optimization Method for Digital Filter Design
Yoon, Sang-Hun ; Chong, Jong-Wha ; Lin, Chi-Ho ;
ETRI Journal, volume 26, issue 6, 2004, Pages 545~545
In this paper, we propose an efficient design method for area optimization in a digital filter. The conventional methods to reduce the number of adders in a filter have the problem of a long critical path delay caused by the deep logic depth of the filter due to adder sharing. Furthermore, there is such a disadvantage that they use the transposed direct form (TDF) filter which needs more registers than those of the direct form (DF) filter. In this paper, we present a hybrid structure of a TDF and DF based on the flattened coefficients method so that it can reduce the number of flip-flops and full-adders without additional critical path delay. We also propose a resource sharing method and sharing-pattern searching algorithm to reduce the number of adders without deepening the logic depth. Simulation results show that the proposed structure can save the number of adders and registers by 22 and 26%, respectively, compared to the best one used in the past.
Design of Dual-Mode Digital Down Converter for WCDMA and cdma2000
Kim, Mi-Yeon ; Lee, Seung-Jun ;
ETRI Journal, volume 26, issue 6, 2004, Pages 555~555
DOI : 10.4218/etrij.04.0804.0013
We propose an efficient digital IF down converter architecture for dual-mode WCDMA/cdma2000 based on the concept of software defined radio. Multi-rate digital filters and fractional frequency conversion techniques are adopted to implement the front end of a dual-mode receiver for WCDMA and cdma2000. A sub-sampled digital IF stage was proposed to support both WCDMA and cdma2000 while lowering the sampling frequency. Use of a CIC filter and ISOP filter combined with proper arrangement of multi-rate filters and common filter blocks resulted in optimized hardware implementation of the front end block in 292k logic gates.
An Analog Front-End Circuit for ISO/IEC 14443-Compatible RFID Interrogators
Min, Kyung-Won ; Chai, Suk-Byung ; Kim, Shi-Ho ;
ETRI Journal, volume 26, issue 6, 2004, Pages 560~560
An analog front-end circuit for ISO/IEC 14443-compatible radio frequency identification (RFID) interrogators was designed and fabricated by using a
double-poly CMOS process. The fabricated chip was operated using a 3.3 Volt single-voltage supply. The results of this work could be provided as reusable IPs in the form of hard or firm IPs for designing single-chip ISO/IEC 14443-compatible RFID interrogators.
An Efficient Scheme to Achieve Differential Unitary Space-Time Modulation on MIMO-OFDM Systems
Liu, Shou-Yin ; Chong, Jong-Wha ;
ETRI Journal, volume 26, issue 6, 2004, Pages 565~565
Differential unitary space-time modulation (DUSTM) has emerged as a promising technique to obtain spatial diversity without intractable channel estimation. This paper presents a study of the application of DUSTM on multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) systems with frequency-selective fading channels. From the view of a correlation analysis between subcarriers of OFDM, we obtain the maximum achievable diversity of DUSTM on MIMO-OFDM systems. Moreover, an efficient implementation strategy based on subcarrier reconstruction is proposed, which transmits all the signals of one signal matrix in one OFDM transmission and performs differential processing between two adjacent OFDM blocks. The proposed method is capable of obtaining both spatial and multipath diversity while reducing the effect of time variation of channels to a minimum. The performance improvement is confirmed by simulation results.
A 15 nm Ultra-thin Body SOI CMOS Device with Double Raised Source/Drain for 90 nm Analog Applications
Park, Chang-Hyun ; Oh, Myung-Hwan ; Kang, Hee-Sung ; Kang, Ho-Kyu ;
ETRI Journal, volume 26, issue 6, 2004, Pages 575~575
Fully-depleted silicon-on-insulator (FD-SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the single- raised (SR) and double-raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self-heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self-heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a
6T-SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra-thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.
Effect of Shield Line on Noise Margin and Refresh Time of Planar DRAM Cell for Embedded Application
Lee, Jung-Hwan ; Jeon, Seong-Do ; Chang, Sung-Keun ;
ETRI Journal, volume 26, issue 6, 2004, Pages 583~583
In this paper we investigate the effect of a shield metal line inserted between adjacent bit lines on the refresh time and noise margin in a planar DRAM cell. The DRAM cell consists of an access transistor, which is biased to 2.5V during operation, and an NMOS capacitor having the capacitance of 10fF per unit cell and a cell size of
. We designed a 1Mb DRAM with an open bit-line structure. It appears that the refresh time is increased from 4.5 ms to 12 ms when the shield metal line is inserted. Also, it appears that no failure occurs when
is increased from 2.2 V to 3 V during a bump up test, while it fails at 2.8 V without a shield metal line. Raphael simulation reveals that the coupling noise between adjacent bit lines is reduced to 1/24 when a shield metal line is inserted, while total capacitance per bit line is increased only by 10%.
Optimization of Packaging Design of TWEAM Module for Digital and Analog Applications
Choi, Kwang-Seong ; Lee, Jong-Hyun ; Lim, Ji-Youn ; Kang, Young-Shik ; Chung, Yong-Duck ; Moon, Jong-Tae ; Kim, Je-Ha ;
ETRI Journal, volume 26, issue 6, 2004, Pages 589~589
Packaging technologies for a broadband and narrowband modulator with a traveling wave electro-absorption modulator (TWEAM) device were developed. In developing a broadband modulator, the effects of the device and packaging designs on the broadband performance were investigated. The optimized designs were obtained through a simulation with the result that we developed a broadband modulator with a 3 dB bandwidth of 38 GHz in the electrical-to-optical (E/O) response, an electrical return loss of less than -10 dB at up to 26 GHz, an rms jitter of 1.832 ps, and an extinction ratio of 5.38 dB in a 40 Gbps non-return to zero (NRZ) eye diagram. For analog application, the effect of the RF termination scheme on the fractional bandwidth was studied. The microstrip line with a double stub as a matching circuit and a laser trimming process were used to obtain an
of -34.58 dB at 40 GHz and 2.9 GHz bandwidth of less than -15 dB.
Virtual Control of Optical Axis of the 3DTV Camera for Reducing Visual Fatigue in Stereoscopic 3DTV
Park, Jong-Il ; Um, Gi-Mun ; Ahn, Chung-Hyun ; Ahn, Chie-Teuk ;
ETRI Journal, volume 26, issue 6, 2004, Pages 597~597
In stereoscopic television, there is a trade-off between visual comfort and 3-dimensional (3D) impact with respect to the baseline-stretch of a 3DTV camera. It is necessary to adjust the baseline-stretch at an appropriate the distance depending on the contents of a scene if we want to obtain a subjectively optimal quality of an image. However, it is very hard to obtain a small baseline-stretch using commercially available cameras of broadcasting quality where the sizes of the lens and CCD module are large. In order to overcome this limitation, we attempt to freely control the baseline-stretch of a stereoscopic camera by synthesizing the virtual views at the desired location of interval between two cameras. This proposed technique is based on the stereo matching and view synthesis techniques. We first obtain a dense disparity map using a hierarchical stereo matching with the edge-adaptive multiple shifted windows. Then, we synthesize the virtual views using the disparity map. Simulation results with various stereoscopic images demonstrate the effectiveness of the proposed technique.
Array Calibration for CDMA Smart Antenna Systems
Kyeong, Mun-Geon ; Park, Hyung-Geun ; Oh, Hyun-Seo ; Jung, Jae-Ho ;
ETRI Journal, volume 26, issue 6, 2004, Pages 605~605
In this paper, we investigate array calibration algorithms to derive a further improved version for correcting antenna array errors and RF transceiver errors in CDMA smart antenna systems. The structure of a multi-channel RF transceiver with a digital calibration apparatus and its calibration techniques are presented, where we propose a new RF receiver calibration scheme to minimize interference of the calibration signal on the user signals. The calibration signal is injected into a multi-channel receiver through a calibration signal injector whose array response vector is controlled in order to have a low correlation with the antenna response vector of the receive signals. We suggest a model-based antenna array calibration to remove the antenna array errors including mutual coupling errors or to predict the element patterns from the array manifold measured at a small number of angles. Computer simulations and experiment results are shown to verify the calibration algorithms.
A Memory-Efficient Block-wise MAP Decoder Architecture
Kim, Sik ; Hwang, Sun-Young ; Kang, Moon-Jun ;
ETRI Journal, volume 26, issue 6, 2004, Pages 615~615
Next generation mobile communication system, such as IMT-2000, adopts Turbo codes due to their powerful error correction capability. This paper presents a block-wise maximum a posteriori (MAP) Turbo decoding structure with a low memory requirement. During this research, it has been observed that the training size and block size determine the amount of required memory and bit-error rate (BER) performance of the block-wise MAP decoder, and that comparable BER performance can be obtained with much shorter blocks when the training size is sufficient. Based on this observation, a new decoding structure is proposed and presented in this paper. The proposed block-wise decoder employs a decoding scheme for reducing the memory requirement by setting the training size to be N times the block size. The memory requirement for storing the branch and state metrics can be reduced 30% to 45%, and synthesis results show that the overall memory area can be reduced by 5.27% to 7.29%, when compared to previous MAP decoders. The decoder throughput can be maintained in the proposed scheme without degrading the BER performance.
Improved Design Criterion for Space-Frequency Trellis Codes over MIMO-OFDM Systems
Liu, Shou-Yin ; Chong, Jong-Wha ;
ETRI Journal, volume 26, issue 6, 2004, Pages 622~622
In this paper, we discuss the design problem and the robustness of space-frequency trellis codes (SFTCs) for multiple input multiple output, orthogonal frequency division multiplexing (MIMO-OFDM) systems. We find that the channel constructed by the consecutive subcarriers of an OFDM block is a correlated fading channel with the regular correlation function of the number and time delay of the multipaths. By introducing the first-order auto-regressive model, we decompose the correlated fading channel into two independent components: a slow fading channel and a fast fading channel. Therefore, the design problem of SFTCs is converted into the joint design in both slow fading and fast fading channels. We present an improved design criterion for SFTCs. We also show that the SFTCs designed according to our criterion are robust against the multipath time delays. Simulation results are provided to confirm our theoretic analysis.
Fractional Multi-bit Differential Detection Technique for Continuous Phase Modulation
Lee, Kee-Hoon ; Seo, Jong-Soo ;
ETRI Journal, volume 26, issue 6, 2004, Pages 635~635
A new low-complexity differential detection technique, fractional multi-bit differential detection (FMDD), is proposed in order to improve the performance of continuous phase modulation (CPM) signals such as Gaussian minimum shift keying (GMSK) and Gaussian frequency shift keying (GFSK). In comparison to conventional one-bit differential detected (1DD) GFSK, the FMDD-employed GFSK provides a signal-to-noise ratio advantage of up to 1.8 dB in an AWGN channel. Thus, the bit-error rate performance of the proposed FMDD is brought close to that of an ideal coherent detection while avoiding the implementation complexity associated with the carrier recovery. In the adjacent channel interference environment, FMDD achieves an even larger SNR advantage compared to 1DD.
Differentiation of Signature Traits
Mobile- and Table-Based Digitizers
Elliott, Stephen J. ;
ETRI Journal, volume 26, issue 6, 2004, Pages 641~641
As the use of signatures for identification purposes is pervasive in society and has a long history in business, dynamic signature verification (DSV) could be an answer to authenticating a document signed electronically and establishing the identity of that document in a dispute. DSV has the advantage in that traits of the signature can be collected on a digitizer. The research question of this paper is to understand how the individual variables vary across devices. In applied applications, this is important because if the signature variables change across the digitizers this will impact performance and the ability to use those variable. Understanding which traits are consistent across devices will aid dynamic signature algorithm designers to create more robust algorithms.
A New Ionic Liquid for a Redox Electrolyte of Dye-Sensitized Solar Cells
Kang, Man-Gu ; Ryu, Kwang-Sun ; Chang, Soon-Ho ; Park, Nam-Gyu ;
ETRI Journal, volume 26, issue 6, 2004, Pages 647~647
A new ionic liquid, 1-vinyl-3-heptylimidazolium iodide (VHpII), was synthesized and applied as a redox electrolyte for dye-sensitized solar cells. The chemical structure of the synthesized VHpII was confirmed using
NMR. Thermogravimetric analysis showed that the VHpII was stable for thermal stress of up to
. The energy conversion efficiencies of the VHpII-based dye-sensitized solar cells were investigated in terms of the effect of a lithium iodide addition. A solar cell containing the redox couple of VHpII and iodine showed a conversion efficiency of 2.63% under 1 sun light intensity at AM 1.5. Adding 0.4 M LiI results in a conversion efficiency of 3.63%, which was an improvement of about 40%. The increased conversion efficiency was ascribed to an increase in external quantum efficiency.
A Novel Method for Inserting an MPEG-2 TS into Ensemble in a DMB Transmission System
Lee, Gwang-Soon ; Bae, Byung-Jun ; Hahm, Young-Kwon ; Lee, Soo-In ;
ETRI Journal, volume 26, issue 6, 2004, Pages 653~653
This paper presents an effective algorithm for inserting an MPEG-2 transport stream (TS) into a Digital Audio Broadcasting (DAB) ensemble without any bandwidth waste in a Digital Multimedia Broadcasting (DMB) transmission system. The key technologies of this algorithm include packet rate control and program clock reference correction, which are important for TS processing. The proposed algorithms are applied to the various DMB transmission systems based on Eureka-147, and the performance of the proposed algorithm is confirmed through the experimental DMB broadcasting.
A Numerically Controlled Oscillator with a Fine Phase Tuner and a Rounding Processor
Lim, In-Gi ; Kim, Whan-Woo ;
ETRI Journal, volume 26, issue 6, 2004, Pages 657~657
We propose a fine phase tuner and a rounding processor for a numerically controlled oscillator (NCO), yielding a reduced phase error in generating a digital sine waveform. By using the fine phase tuner presented in this paper, when the ratio of the desired sine wave frequency to the clock frequency is expressed as a fraction, an accurate adjustment in representing the fractional value can be achieved with simple hardware. In addition, the proposed rounding processor reduces the effects of phase truncation on the output spectrum. Logic simulation results of the NCO using these techniques show that the noise spectrum and mean square error (MSE) for eight output bits of a 3.125 MHz sine waveform are reduced by 8.68 dB and 5.5 dB, respectively, compared to those of the truncation method, and 2.38 dB and 0.83 dB, respectively, compared to those of Paul's scheme.
Thermal Behavior of Arrayed-Waveguide Grating Made of Silica/Polymer Hybrid Waveguide
Kim, Duk-Jun ; Shin, Jang-Uk ; Han, Young-Tak ; Park, Sang-Ho ; Park, Yun-Jung ; Sung, Hee-Kyung ; Kim, Dong-Kun ;
ETRI Journal, volume 26, issue 6, 2004, Pages 661~661
The thermal behavior of an arrayed-waveguide grating made of a silica/polymer hybrid waveguide was examined. We experimentally confirmed that the hybrid waveguide is effective to decrease the temperature and polarization dependence of the center wavelength owing to the negative thermo-optic coefficient of the refractive index and extremely low baking temperature of the polymer cladding. However, the detachment of the polymer cladding from the silica core, which took place either during a repeated heat cycle test or during long-term storage in atmosphere, was a serious problem for practical use.
Determination of the Optimal Access Charge for the Mobile Virtual Network Operator System
Kim, Byung-Woon ; Park, Sung-Uk ;
ETRI Journal, volume 26, issue 6, 2004, Pages 665~665
The introduction of a mobile virtual network operator (MVNO) system is expected to increase consumer benefits, boost competition in the mobile market, utilize idle bandwidth, and expedite mobile-fixed line convergence and growth in the mobile Internet market. This research endeavors to study the optimal access charge for an MVNO system, which is expected to be introduced to the Korean mobile communications market. We found that the optimal access charge is higher in the interdependent model than in the independent model if demand for mobile phone service is based on a substitution relationship. We also found that the optimal access charge is higher than the marginal cost.
Single-Electron Pass-Transistor Logic with Multiple Tunnel Junctions and Its Hybrid Circuit with MOSFETs
Cho, Young-Kyun ; Jeong, Yoon-Ha ;
ETRI Journal, volume 26, issue 6, 2004, Pages 669~669
To improve the operation error caused by the thermal fluctuation of electrons, we propose a novel single-electron pass-transistor logic circuit employing a multiple-tunnel junction (MTJ) scheme and modulate a parameters of an MTJ single-electron tunneling device (SETD) such as the number of tunnel junctions, tunnel resistance, and voltage gain. The operation of a 3-MTJ inverter circuit is simulated at 15 K with parameters
. Using the SETD/MOSFET hybrid circuit, the charge state output of the proposed MTJ-SETD logic is successfully translated to the voltage state logic.