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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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Journal DOI :
Electronics and Telecommunications Research Institute
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Volume & Issues
Volume 27, Issue 6 - Dec 2005
Volume 27, Issue 5 - Oct 2005
Volume 27, Issue 4 - Aug 2005
Volume 27, Issue 3 - Jun 2005
Volume 27, Issue 2 - Apr 2005
Volume 27, Issue 1 - Feb 2005
Selecting the target year
Fully Differential 5-GHz LC-Tank VCOs with Improved Phase Noise and Wide Tuning Range
Lee, Ja-Yol ; Park, Chan-Woo ; Lee, Sang-Heung ; Kang, Jin-Young ; Oh, Seung-Hyeub ;
ETRI Journal, volume 27, issue 5, 2005, Pages 473~473
In this paper, we propose two LC voltage-controlled oscillators (VCOs) that improve both phase noise and tuning range. With both 1/f induced low-frequency noise and low-frequency thermal noise around DC or around harmonics suppressed significantly by the employment of a current-current negative feedback (CCNF) loop, the phase noise in the CCNF LC VCO has been improved by about 10 dB at 6 MHz offset compared to the conventional LC VCO. The phase noise of the CCNF VCO was measured as -112 dBc/Hz at 6 MHz offset from 5.5 GHz carrier frequency. Also, we present a bandwidth-enhanced LC VCO whose tuning range has been increased about 250 % by connecting the varactor to the bases of the cross-coupled pair. The phase noise of the bandwidth-enhanced LC-tank VCO has been improved by about 6 dB at 6 MHz offset compared to the conventional LC VCO. The phase noise reduction has been achieved because the DC-decoupling capacitor Cc prevents the output common-mode level from modulating the varactor bias point, and the signal power increases in the LC-tank resonator. The bandwidth-enhanced LC VCO represents a 12 % bandwidth and phase noise of -108 dBc/Hz at 6 MHz offset.
Fabrication of 40 Gb/s Front-End Optical Receivers Using Spot-Size Converter Integrated Waveguide Photodiodes
Kwon, Yong-Hwan ; Choe, Joong-Seon ; Kim, Je-Ha ; Kim, Ki-Soo ; Choi, Kwang-Seong ; Choi, Byung-Seok ; Yun, Ho-Gyeong ;
ETRI Journal, volume 27, issue 5, 2005, Pages 484~484
We fabricated 40 Gb/s front-end optical receivers using spot-size converter integrated waveguide photodiodes (SSC-WGPDs). The fabricated SSC-WGPD chips showed a high responsivity of approximately 0.8 A/W and a 3 dB bandwidth of approximately 40 GHz. A selective wet-etching method was first adopted to realize the required width and depth of a tapered waveguide. Two types of electrical pre-amplifier chips were used in our study. One has higher gain and the other has a broader bandwidth. The 3 dB bandwidths of the higher gain and broader bandwidth modules were about 32 and 42 GHz, respectively. Clear 40 Gb/s non-return-to-zero (NRZ) eye diagrams showed good system applicability of these modules.
Application Specific Processor Design for H.264 Decoder with a Configurable Embedded Processor
Han, Jin-Ho ; Lee, Mi-Young ; Bae, Young-Hwan ; Cho, Han-Jin ;
ETRI Journal, volume 27, issue 5, 2005, Pages 491~491
An application specific processor for an H.264 decoder with a configurable embedded processor is designed in this research. The motion compensation, inverse integer transform, inverse quantization, and entropy decoding algorithm of H.264 decoder software are optimized. We improved the performance of the processor with instruction-level hardware optimization, which is tailored to configurable embedded processor architecture. The optimized instructions for video processing can be used in other video compression standards such as MPEG 1, 2, and 4. A significant performance improvement is achieved with high flexibility. Experimental results show that we could achieve 300% performance for the H.264 baseline profile level 2 decoder.
Performance Analysis for MPEG-4 Video Codec Based on On-Chip Network
Chang, June-Young ; Kim, Won-Jong ; Bae, Young-Hwan ; Han, Jin-Ho ; Cho, Han-Jin ; Jung, Hee-Bum ;
ETRI Journal, volume 27, issue 5, 2005, Pages 497~497
In this paper, we present a performance analysis for an MPEG-4 video codec based on the on-chip network communication architecture. The existing on-chip buses of system-on-a-chip (SoC) have some limitation on data traffic bandwidth since a large number of silicon IPs share the bus. An on-chip network is introduced to solve the problem of on-chip buses, in which the concept of a computer network is applied to the communication architecture of SoC. We compared the performance of the MPEG-4 video codec based on the on-chip network and Advanced Micro-controller Bus Architecture (AMBA) on-chip bus. Experimental results show that the performance of the MPEG-4 video codec based on the on-chip network is improved over 50% compared to the design based on a multi-layer AMBA bus.
Low-Power Video Decoding on a Variable Voltage Processor for Mobile Multimedia Applications
Lee, Seong-Soo ;
ETRI Journal, volume 27, issue 5, 2005, Pages 504~504
This paper proposes a novel low-power video decoding scheme. In the encoded video bitstream, there is quite a large number of non-coded blocks. When the number of the non-coded blocks in a frame is known at the start of frame decoding, the workload of the video decoding can be estimated. Consequently, the supply voltage of very large-scale integration (VLSI) circuits can be lowered, and the power consumption can be reduced. In the proposed scheme, the encoder counts the number of non-coded blocks and stores this information in the frame header of the bitstream. Simulation results show that the proposed scheme reduces the power consumption to about 1/10 to 1/20.
An Efficient Hardware Architecture of Intra Prediction and TQ/IQIT Module for H.264 Encoder
Suh, Ki-Bum ; Park, Seong-Mo ; Cho, Han-Jin ;
ETRI Journal, volume 27, issue 5, 2005, Pages 511~511
In this paper, we propose a novel hardware architecture for an intra-prediction, integer transform, quantization, inverse integer transform, inverse quantization, and mode decision module for the macroblock engine of a new video coding standard, H.264. To reduce the cycle of intra prediction, transform/quantization, and inverse quantization/inverse transform of H.264, a reduction method for cycle overhead in the case of I16MB mode is proposed. This method can process one macroblock for 927 cycles for all cases of macroblock type by processing
Hadamard transform and quantization during
prediction. This module was designed using Verilog Hardware Description Language (HDL) and operates with a 54 MHz clock using the Hynix
TLM (triple layer metal) library.
Design and Architecture of Low-Latency High-Speed Turbo Decoders
Jung, Ji-Won ; Lee, In-Ki ; Choi, Duk-Gun ; Jeong, Jin-Hee ; Kim, Ki-Man ; Choi, Eun-A ; Oh, Deock-Gil ;
ETRI Journal, volume 27, issue 5, 2005, Pages 525~525
In this paper, we propose and present implementation results of a high-speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix-4, center to top, parallel decoding, and early-stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real-time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix-4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field-programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.
Pipelined Scheduling of Functional HW/SW Modules for Platform-Based SoC Design
Kim, Won-Jong ; Chang, June-Young ; Cho, Han-Jin ;
ETRI Journal, volume 27, issue 5, 2005, Pages 533~533
We developed a pipelined scheduling technique of functional hardware and software modules for platform-based system-on-a-chip (SoC) designs. It is based on a modified list scheduling algorithm. We used the pipelined scheduling technique for a performance analysis of an MPEG4 video encoder application. Then, we applied it for architecture exploration to achieve a better performance. In our experiments, the modified SoC platform with 6 pipelines for the 32-bit dual layer architecture shows a 118% improvement in performance compared to the given basic SoC platform with 4 pipelines for the 16-bit single-layer architecture.
A Low Power Analog CMOS Vision Chip for Edge Detection Using Electronic Switches
Kim, Jung-Hwan ; Kong, Jae-Sung ; Suh, Sung-Ho ; Lee, Min-Ho ; Shin, Jang-Kyoo ; Park, Hong-Bae ; Choi, Chang-Auck ;
ETRI Journal, volume 27, issue 5, 2005, Pages 539~539
An analog CMOS vision chip for edge detection with power consumption below 20mW was designed by adopting electronic switches. An electronic switch separates the edge detection circuit into two parts; one is a logarithmic compression photocircuit, the other is a signal processing circuit for edge detection. The electronic switch controls the connection between the two circuits. When the electronic switch is OFF, it can intercept the current flow through the signal processing circuit and restrict the magnitude of the current flow below several hundred nA. The estimated power consumption of the chip, with
pixels, was below 20mW. The vision chip was designed using
1-poly 5-metal standard full custom CMOS process technology.
Ultra Thin Film Encapsulation of Organic Light Emitting Diode on a Plastic Substrate
Park, Sang-Hee ; Oh, Ji-Young ; Hwang, Chi-Sun ; Lee, Jeong-Ik ; Yang, Yong-Suk ; Chu, Hye-Yong ; Kang, Kwang-Yong ;
ETRI Journal, volume 27, issue 5, 2005, Pages 545~545
We have carried out the fabrications of a barrier layer on a polyethersulfon (PES) film and organic light emitting diode (OLED) based on a plastic substrate by means of atomic layer deposition (ALD). Simultaneous deposition of 30 nm
film on both sides of the PES film gave a water vapor transition rate (WVTR) of
. Further, the double layer of 200 nm
film deposited by plasma enhanced chemical vapor deposition (PECVD) and 20 nm
film by ALD resulted in a WVTR value lower than the detection limit of MOCON. We have investigated the OLED encapsulation performance of the double layer using the OLED structure of ITO / MTDATA (20 nm) / NPD (40 nm) / AlQ (60 nm) / LiF (1 nm) / Al (75 nm) on a plastic substrate. The preliminary life time to reach 91% of the initial luminance
was 260 hours for the OLED encapsulated with 100 nm of PECVD-deposited
and 30 nm of ALD-deposited
Fabrication of Butt-Coupled SGDBR Laser Integrated with Semiconductor Optical Amplifier Having a Lateral Tapered Waveguide
Oh, Su-Hwan ; Ko, Hyun-Sung ; Kim, Ki-Soo ; Lee, Ji-Myon ; Lee, Chul-Wook ; Kwon, Oh-Kee ; Park, Sahng-Gii ; Park, Moon-Ho ;
ETRI Journal, volume 27, issue 5, 2005, Pages 551~551
We have demonstrated a high-power widely tunable sampled grating distributed Bragg reflector (SGDBR) laser integrated monolithically with a semiconductor optical amplifier (SOA) having a lateral tapered waveguide, which is the first to emit a fiber-coupled output power of more than 10 dBm using a planar buried heterostructure (PBH). The output facet reflectivity of the integrated SOA using a lateral tapered waveguide and two-layer AR coating of
was lower than
a wide bandwidth of 85 nm. The spectra of 40 channels spaced by 50 GHz within the tuning range of 33 nm were obtained by a precise control of SG and phase control currents. A side-mode suppression ratio of more than 35 dB was obtained in the whole tuning range. Fiber-coupled output power of more than 11 dBm and an output power variation of less than 1 dB were obtained for the whole tuning range.
Design of Encoder and Decoder for LDPC Codes Using Hybrid H-Matrix
Lee, Chan-Ho ;
ETRI Journal, volume 27, issue 5, 2005, Pages 557~557
Low-density parity-check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and are synthesized using a
CMOS standard cell library.
A Motion-Control Chip to Generate Velocity Profiles of Desired Characteristics
Cho, Jung-Uk ; Jeon, Jae-Wook ;
ETRI Journal, volume 27, issue 5, 2005, Pages 563~563
A motion-control chip contains major functions that are necessary to control the position of each motor, such as generating velocity command profiles, reading motor positions, producing control signals, driving several types of servo amplifiers, and interfacing host processors. Existing motion-control chips can only generate velocity profiles of fixed characteristics, typically linear and s-shape smooth symmetric curves. But velocity profiles of these two characteristics are not optimal for all tasks in industrial robots and automation systems. Velocity profiles of other characteristics are preferred for some tasks. This paper proposes a motion-control chip to generate velocity profiles of desired acceleration and deceleration characteristics. The proposed motion-control chip is implemented with a field-programmable gate array by using the Very High-Speed Integrated Circuit Hardware Description Language and Handel-C. Experiments using velocity profiles of four different characteristics will be performed.
Monolithic SiGe Up-/Down-Conversion Mixers with Active Baluns
Lee, Sang-Heung ; Lee, Seung-Yun ; Bae, Hyun-Cheol ; Lee, Ja-Yol ; Kim, Sang-Hoon ; Kim, Bo-Woo ; Kang, Jin-Yeong ;
ETRI Journal, volume 27, issue 5, 2005, Pages 569~569
The purpose of this paper is to describe the implementation of monolithically matching circuits, interface circuits, and RF core circuits to the same substrate. We designed and fabricated on-chip 1 to 6 GHz up-conversion and 1 to 8 GHz down-conversion mixers using a 0.8 mm SiGe hetero-junction bipolar transistor (HBT) process technology. To fabricate a SiGe HBT, we used a reduced pressure chemical vapor deposition (RPCVD) system to grow a base epitaxial layer, and we adopted local oxidation of silicon (LOCOS) isolation to separate the device terminals. An up-conversion mixer was implemented on-chip using an intermediate frequency (IF) matching circuit, local oscillator (LO)/radio frequency (RF) wideband matching circuits, LO/IF input balun circuits, and an RF output balun circuit. The measured results of the fabricated up-conversion mixer show a positive power conversion gain from 1 to 6 GHz and a bandwidth of about 4.5 GHz. Also, the down-conversion mixer was implemented on-chip using LO/RF wideband matching circuits, LO/RF input balun circuits, and an IF output balun circuit. The measured results of the fabricated down-conversion mixer show a positive power conversion gain from 1 to 8 GHz and a bandwidth of about 4.5 GHz.
A Single Transistor-Level Direct-Conversion Mixer for Low-Voltage Low-Power Multi-band Radios
Choi, Byoung-Gun ; Hyun, Seok-Bong ; Tak, Geum-Young ; Lee, Hee-Tae ; Park, Seong-Su ; Park, Chul-Soon ;
ETRI Journal, volume 27, issue 5, 2005, Pages 579~579
A CMOS direct-conversion mixer with a single transistor-level topology is proposed in this paper. Since the single transistor-level topology needs smaller supply voltage than the conventional Gilbert-cell topology, the proposed mixer structure is suitable for a low power and highly integrated RF system-on-a-chip (SoC). The proposed direct-conversion mixer is designed for the multi-band ultra-wideband (UWB) system covering from 3 to 7 GHz. The conversion gain and input P1dB of the mixer are about 3 dB and -10 dBm, respectively, with multi-band RF signals. The mixer consumes 4.3 mA under a 1.8 V supply voltage.
Miniaturized Electronic Nose System Based on a Personal Digital Assistant
Kim, Yong-Shin ; Yang, Yoon-Seok ; Ha, Seung-Chul ; Pyo, Hyeon-Bong ; Choi, Auck-Choi ;
ETRI Journal, volume 27, issue 5, 2005, Pages 585~585
A small electronic nose (E-Nose) system has been developed using an 8-channel vapor detection array and personal digital assistant (PDA). The sensor array chip, integrated on a single microheater-embedded polyimide substrate, was made of carbon black-polymer composites with different kinds of polymers and plasticizers. We have successfully classified various volatile organic compounds such as methanol, ethanol, i-propanol, benzene, toluene, n-hexane, n-heptane, and c-hexane with the aid of the sensor array chip, and have evaluated the resolution factors among them, quantitatively. To achieve a PDA-based E-Nose system, we have also elaborated small sensor-interrogating circuits, simple vapor delivery components, and data acquisition and processing programs. As preliminary results show, the miniaturized E-Nose system has demonstrated the identification of essential oils extracted from mint, lavender, and eucalyptus plants.
Protection of MPEG-2 Multicast Streaming in an IP Set-Top Box Environment
Hwang, Seong-Oun ; Kim, Jeong-Hyon ; Nam, Do-Won ; Yoon, Ki-Song ;
ETRI Journal, volume 27, issue 5, 2005, Pages 595~595
The widespread use of the Internet has led to the problem of intellectual property and copyright infringement. Digital rights management (DRM) technologies have been developed to protect digital content items. Digital content can be classified into static content (for example, text or media files) and dynamic content (for example, VOD or multicast streams). This paper deals with the protection of a multicast stream on set-top boxes connected to an IP network. In this paper, we examine the following design and architectural issues to be considered when applying DRM functions to multicast streaming service environments: transparent streaming service and large-scale user environments. To address the transparency issue, we introduce a 'selective encryption scheme'. To address the second issue, a 'key packet insertion scheme' and 'hierarchical key management scheme' are introduced. Based on the above design and architecture, we developed a prototype of a multicasting DRM system. The analysis of our implementation shows that it supports transparent and scalable DRM multicasting service in a large-scale user environment.
Audio Watermarking through Modification of Tonal Maskers
Lee, Hee-Suk ; Lee, Woo-Sun ;
ETRI Journal, volume 27, issue 5, 2005, Pages 608~608
Watermarking has become a technology of choice for a broad range of multimedia copyright protection applications. This paper proposes an audio watermarking scheme that uses the modified tonal masker as an embedding carrier for imperceptible and robust audio watermarking. The method of embedding is to select one of the tonal maskers using a secret key, and to then modify the frequency signals that consist of the tonal masker without changing the sound pressure level. The modified tonal masker can be found using the same secret key without the original sound, and the embedded information can be extracted. The results show that the frequency signals are stable enough to keep embedded watermarks against various common signal processing types, while at the same time the proposed scheme has a robust performance.
Speeding up Scalar Multiplication in Genus 2 Hyperelliptic Curves with Efficient Endomorphisms
Park, Tae-Jun ; Lee, Mun-Kyu ; Park, Kun-Soo ; Chung, Kyo-Il ;
ETRI Journal, volume 27, issue 5, 2005, Pages 617~617
This paper proposes an efficient scalar multiplication algorithm for hyperelliptic curves, which is based on the idea that efficient endomorphisms can be used to speed up scalar multiplication. We first present a new Frobenius expansion method for special hyperelliptic curves that have Gallant-Lambert-Vanstone (GLV) endomorphisms. To compute kD for an integer k and a divisor D, we expand the integer k by the Frobenius endomorphism and the GLV endomorphism. We also present improved scalar multiplication algorithms that use the new expansion method. By our new expansion method, the number of divisor doublings in a scalar multiplication is reduced to a quarter, while the number of divisor additions is almost the same. Our experiments show that the overall throughputs of scalar multiplications are increased by 15.6 to 28.3 % over the previous algorithms when the algorithms are implemented over finite fields of odd characteristics.
AC Modeling of the ggNMOS ESD Protection Device
Choi, Jin-Young ;
ETRI Journal, volume 27, issue 5, 2005, Pages 628~628
From AC analysis results utilizing a 2-dimensional device simulator, we extracted an AC-equivalent circuit of a grounded-gate NMOS (ggNMOS) electrostatic discharge (ESD) protection device. The extracted equivalent circuit is utilized to analyze the effects of the parasitics in a ggNMOS protection device on the characteristics of a low noise amplifier (LNA). We have shown that the effects of the parasitics can appear exaggerated for an impedance matching aspect and that the noise contribution of the parasitic resistances cannot be counted if the ggNMOS protection device is modeled by a single capacitor, as in prior publications. We have confirmed that the major changes in the characteristics of an LNA when connecting an NMOS protection device at the input are reduction of the power gain and degradation of the noise performance. We have also shown that the performance degradation worsens as the substrate resistance is reduced, which could not be detected if a single capacitor model is used.
Multi-channel Audio Service in a Terrestrial-DMB System Using VSLI-Based Spatial Audio Coding
Seo, Jeong-Il ; Moon, Han-Gil ; Beack, Seung-Kwon ; Kang, Kyeong-Ok ; Hong, Jae-Keun ;
ETRI Journal, volume 27, issue 5, 2005, Pages 635~635
Spatial audio coding (SAC) is an extremely high compact representation of encoded multi-channel audio material. This paper suggests a multi-channel audio service in the terrestrial digital multimedia broadcasting (T-DMB) system using a novel SAC tool, which is called a virtual source location information (VSLI)-based SAC tool. Intensive experiments are presented to evaluate the validity of the proposed VSLI-based SAC tool, and prototypical systems are also presented to demonstrate the reliability of the proposed multi-channel T-DMB system in real applications.
Complexity-Reduced Algorithms for LDPC Decoder for DVB-S2 Systems
Choi, Eun-A ; Jung, Ji-Won ; Kim, Nae-Soo ; Oh, Deock-Gil ;
ETRI Journal, volume 27, issue 5, 2005, Pages 639~639
This paper proposes two kinds of complexity-reduced algorithms for a low density parity check (LDPC) decoder. First, sequential decoding using a partial group is proposed. It has the same hardware complexity and requires a fewer number of iterations with little performance loss. The amount of performance loss can be determined by the designer, based on a tradeoff with the desired reduction in complexity. Second, an early detection method for reducing the computational complexity is proposed. Using a confidence criterion, some bit nodes and check node edges are detected early on during decoding. Once the edges are detected, no further iteration is required; thus early detection reduces the computational complexity.
A Narrow Bandwidth Microstrip Band-Pass Filter with Symmetrical Frequency Characteristics
Jun, Dong-Suk ; Lee, Hong-Yeol ; Kim, Dong-Young ; Lee, Sang-Seok ; Nam, Eun-Soo ;
ETRI Journal, volume 27, issue 5, 2005, Pages 643~643
This letter proposes a band-pass filter (BPF) with two transmission zeros based on a combination of parallel coupling and end coupling of half-wave transmission lines. The fabricated BPF exhibited a narrow bandwidth and two transmission zeros near the pass-band due to the end-coupled and shielding waveguide. At the center operation frequency of 60 GHz, the 20 dB bandwidth of the BPF is 1.0 GHz, which is almost 2% of the center operation frequency, and the insertion loss is 3.12 dB. Two transmission zeros reach approximately 40 dB at 58.5 and 62.5 GHz. The simulation results almost agree with the measured results.
Realization of n-th Order Voltage Transfer Function Using a Single Operational Transresistance Amplifier
Kilinc, Selcuk ; Cam, Ugur ;
ETRI Journal, volume 27, issue 5, 2005, Pages 647~647
A new configuration to realize the most general n-th order voltage transfer function is proposed. It employs only one operational transresistance amplifier (OTRA) as the active element. In the synthesis of the transfer function, the RC:-RC decomposition technique is used. To the best of author's knowledge, this is the first topology to be used in the realization of n-th order transfer function employing single OTRA.