Go to the main menu
Skip to content
Go to bottom
REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
Journal Basic Information
Journal DOI :
Electronics and Telecommunications Research Institute
Editor in Chief :
Volume & Issues
Volume 30, Issue 6 - Dec 2008
Volume 30, Issue 5 - Oct 2008
Volume 30, Issue 4 - Aug 2008
Volume 30, Issue 3 - Jun 2008
Volume 30, Issue 2 - Apr 2008
Volume 30, Issue 1 - Feb 2008
Selecting the target year
Initial Timing Acquisition for Binary Phase-Shift Keying Direct Sequence Ultra-wideband Transmission
Kang, Kyu-Min ; Choi, Sang-Sung ;
ETRI Journal, volume 30, issue 4, 2008, Pages 495~505
This paper presents a parallel processing searcher structure for the initial synchronization of a direct sequence ultra-wideband (DS-UWB) system, which is suitable for the digital implementation of baseband functionalities with a 1.32 Gsample/s chip rate analog-to-digital converter. An initial timing acquisition algorithm and a data demodulation method are also studied. The proposed searcher effectively acquires initial symbol and frame timing during the preamble transmission period. A hardware efficient receiver structure using 24 parallel digital correlators for binary phase-shift keying DS-UWB transmission is presented. The proposed correlator structure operating at 55 MHz is shared for correlation operations in a searcher, a channel estimator, and the demodulator of a RAKE receiver. We also present a pseudo-random noise sequence generated with a primitive polynomial,
, for packet detection, automatic gain control, and initial timing acquisition. Simulation results show that the performance of the proposed parallel processing searcher employing the presented pseudo-random noise sequence outperforms that employing a preamble sequence in the IEEE 802.15.3a DS-UWB proposal.
Error Concealment Using Intra-Mode Information Included in H.264/AVC-Coded Bitstream
Kim, Dong-Hyung ; Jeong, Se-Yoon ; Choi, Jin-Soo ; Jeon, Gwang-Gil ; Kim, Seung-Jong ; Jeong, Je-Chang ;
ETRI Journal, volume 30, issue 4, 2008, Pages 506~515
The H.264/AVC standard has adopted new coding tools such as intra-prediction, variable block size, motion estimation with quarter-pixel-accuracy, loop filter, and so on. The adoption of these tools enables an H.264/AVC-coded bitstream to have more information than was possible with previous standards. In this paper, we propose an effective spatial error concealment method with low complexity in H.264/AVC intra-frame. From information included in an H.264/AVC-coded bitstream, we use prediction modes of intra-blocks to recover a damaged block. This is because the prediction direction in each prediction mode is highly correlated to the edge direction. We first estimate the edge direction of a damaged block using the prediction modes of the intra-blocks adjacent to a damaged block and classify the area inside the damaged block into edge and flat areas. Our method then recovers pixel values in the edge area using edge-directed interpolation, and recovers pixel values in the flat area using weighted interpolation. Simulation results show that the proposed method yields better video quality than conventional approaches.
SOI CMOS-Based Smart Gas Sensor System for Ubiquitous Sensor Networks
Maeng, Sung-Lyul ; Guha, Prasanta ; Udrea, Florin ; Ali, Syed Z. ; Santra, Sumita ; Gardner, Julian ; Park, Jong-Hyurk ; Kim, Sang-Hyeob ; Moon, Seung-Eon ; Park, Kang-Ho ; Kim, Jong-Dae ; Choi, Young-Jin ; Milne, William I. ;
ETRI Journal, volume 30, issue 4, 2008, Pages 516~525
This paper proposes a compact, energy-efficient, and smart gas sensor platform technology for ubiquitous sensor network (USN) applications. The compact design of the platform is realized by employing silicon-on-insulator (SOI) technology. The sensing element is fully integrated with SOI CMOS circuits for signal processing and communication. Also, the micro-hotplate operates at high temperatures with extremely low power consumption, which is important for USN applications. ZnO nanowires are synthesized onto the micro-hotplate by a simple hydrothermal process and are patterned by a lift-off to form the gas sensor. The sensor was operated at
and showed a good response to 100 ppb
CMOS UWB RF Transmitter with an On-Chip T/R Switch
Kim, Chang-Wan ; Duong, Quoc-Hoang ; Lee, Seung-Sik ; Lee, Sang-Gug ;
ETRI Journal, volume 30, issue 4, 2008, Pages 526~534
This paper presents a fully integrated 0.13
CMOS MB-OFDM UWB transmitter chain (mode 1). The proposed transmitter consists of a low-pass filter, a variable gain amplifier, a voltage-to-current converter, an I/Q up-mixer, a differential-to-single-ended converter, a driver amplifier, and a transmit/receive (T/R) switch. The proposed T/R switch shows an insertion loss of less than 1.5 dB and a Tx/Rx port isolation of more than 27 dB over a 3 GHz to 5 GHz frequency range. All RF/analog circuits have been designed to achieve high linearity and wide bandwidth. The proposed transmitter is implemented using IBM 0.13
CMOS technology. The fabricated transmitter shows a -3 dB bandwidth of 550 MHz at each sub-band center frequency with gain flatness less than 1.5 dB. It also shows a power gain of 0.5 dB, a maximum output power level of 0 dBm, and output IP3 of +9.3 dBm. It consumes a total of 54 mA from a 1.5 V supply.
Systematic Design of High-Resolution High-Frequency Cascade Continuous-Time Sigma-Delta Modulators
Tortosa, Ramon ; Castro-Lopez, Rafael ; De La Rosa, J.M. ; Roca, Elisenda ; Rodriguez-Vazquez, Angel ; Fernandez, F.V. ;
ETRI Journal, volume 30, issue 4, 2008, Pages 535~545
This paper introduces a systematic top-down and bottom-up design methodology to assist the designer in the implementation of continuous-time (CT) cascade sigma-delta (
) modulators. The salient features of this methodology are (a) flexible behavioral modeling for optimum accuracy-efficiency trade-offs at different stages of the top-down synthesis process, (b) direct synthesis in the continuous-time domain for minimum circuit complexity and sensitivity, (c) mixed knowledge-based and optimization-based architectural exploration and specification transmission for enhanced circuit performance, and (d) use of Pareto-optimal fronts of building blocks to reduce re-design iterations. The applicability of this methodology will be illustrated via the design of a 12-bit 20 MHz CT
modulator in a 1.2 V 130 nm CMOS technology.
Fault Classification in Phase-Locked Loops Using Back Propagation Neural Networks
Ramesh, Jayabalan ; Vanathi, Ponnusamy Thangapandian ; Gunavathi, Kandasamy ;
ETRI Journal, volume 30, issue 4, 2008, Pages 546~554
Phase-locked loops (PLLs) are among the most important mixed-signal building blocks of modern communication and control circuits, where they are used for frequency and phase synchronization, modulation, and demodulation as well as frequency synthesis. The growing popularity of PLLs has increased the need to test these devices during prototyping and production. The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. This is because most analog and mixed signal circuits are tested by their functionality, which is both time consuming and expensive. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques can be employed to automate fault classification. As a possible solution, we use the back propagation neural network (BPNN) to classify the faults in the designed charge-pump PLL. In order to classify the faults, the BPNN was trained with various training algorithms and their performance for the test structure was analyzed. The proposed method of fault classification gave fault coverage of 99.58%.
An Effective Test and Diagnosis Algorithm for Dual-Port Memories
Park, Young-Kyu ; Yang, Myung-Hoon ; Kim, Yong-Joon ; Lee, Dae-Yeal ; Kang, Sung-Ho ;
ETRI Journal, volume 30, issue 4, 2008, Pages 555~564
This paper proposes a test algorithm that can detect and diagnose all the faults occurring in dual-port memories that can be accessed simultaneously through two ports. In this paper, we develop a new diagnosis algorithm that classifies faults in detail when they are detected while the test process is being developed. The algorithm is particularly efficient because it uses information that can be obtained by test results as well as results using an additional diagnosis pattern. The algorithm can also diagnose various fault models for dual-port memories.
Interoperable DRM Framework for Multiple Devices Environment
Hwang, Seong-Oun ; Yoon, Ki-Song ;
ETRI Journal, volume 30, issue 4, 2008, Pages 565~575
As networks increase and cross-convergence occurs between various types of devices and communications, there is an increasing demand for interoperable service in the business environment and from end users. In this paper, we investigate interoperability issues in the digital rights management (DRM) and present a practical framework to support interoperability in environments with multiple devices. The proposed architecture enables end users to consume digital content on all their devices without awareness of the underlying DRM schemes or technologies. It also enables DRM service providers to achieve interoperability without costly modification of their DRM schemes.
Exploiting Thread-Level Parallelism in Lockstep Execution by Partially Duplicating a Single Pipeline
Oh, Jaeg-Eun ; Hwang, Seok-Joong ; Nguyen, Huong Giang ; Kim, A-Reum ; Kim, Seon-Wook ; Kim, Chul-Woo ; Kim, Jong-Kook ;
ETRI Journal, volume 30, issue 4, 2008, Pages 576~586
In most parallel loops of embedded applications, every iteration executes the exact same sequence of instructions while manipulating different data. This fact motivates a new compiler-hardware orchestrated execution framework in which all parallel threads share one fetch unit and one decode unit but have their own execution, memory, and write-back units. This resource sharing enables parallel threads to execute in lockstep with minimal hardware extension and compiler support. Our proposed architecture, called multithreaded lockstep execution processor (MLEP), is a compromise between the single-instruction multiple-data (SIMD) and symmetric multithreading/chip multiprocessor (SMT/CMP) solutions. The proposed approach is more favorable than a typical SIMD execution in terms of degree of parallelism, range of applicability, and code generation, and can save more power and chip area than the SMT/CMP approach without significant performance degradation. For the architecture verification, we extend a commercial 32-bit embedded core AE32000C and synthesize it on Xilinx FPGA. Compared to the original architecture, our approach is 13.5% faster with a 2-way MLEP and 33.7% faster with a 4-way MLEP in EEMBC benchmarks which are automatically parallelized by the Intel compiler.
Market Efficiency Analysis between Facility-Based and Service-Based Competition
Seo, Il-Won ; Lee, Duk-Hee ; Kim, Byung-Woon ;
ETRI Journal, volume 30, issue 4, 2008, Pages 587~596
Facility-based competition (FBC) in the telecommunications market is considered to have lower static efficiency in the short term and higher dynamic efficiency in the long term. Under service-based competition (SBC), the entrant can reduce its setup costs by leasing network facilities from the incumbent, which makes the entrant viable, pushes the market price down and promotes static efficiency. This paper attempts to measure static efficiency by comparing the profits of the incumbent and entrant in terms of consumer surplus and social welfare under each competition type by extending the Stackelberg model. The results, assuming a linear demand function and variation in regulatory level, show that FBC results in higher social welfare than SBC on the whole. However, SBC accompanied by strong regulation is also shown to have the potential to be superior over FBC. It is also revealed that FBC exhibits a higher producer surplus (particularly, the incumbent's producer surplus) and is, therefore, more desirable in terms of dynamic efficiency. When the entrant's cost is high in FBC, social welfare is shown to be lowered, implying that cost competitiveness is a necessary condition for social welfare.
RFID Tag Antenna Coupled by Shorted Microstrip Line for Metallic Surfaces
Choi, Won-Kyu ; Kim, Jeong-Seok ; Bae, Ji-Hoon ; Choi, Gil-Young ; Pyo, Cheol-Sig ; Chae, Jong-Suk ;
ETRI Journal, volume 30, issue 4, 2008, Pages 597~599
This letter presents the design of a small and low-profile RFID tag antenna in the UHF band that can be mounted on metallic objects. The designed tag antenna, which uses a ceramic material as a substrate, consists of a radiating patch and a microstrip line with two shorting pins for a proximity-coupled feeding structure. Using this structure, impedance matching can be simply obtained between the antenna and tag chip without a matching network. The fractional impedance bandwidth for
<3 dB and radiation efficiency are about 1.4% and 56% at 911 MHz, respectively. The read range is approximately from 5 m to 6 m when the tag antenna is mounted on a metallic surface.
Shorted Microstrip Patch Antenna Using Inductively Coupled Feed for UHF RFID Tag
Kim, Jeong-Seok ; Choi, Won-Kyu ; Choi, Gil-Young ; Pyo, Cheol-Sig ; Chae, Jong-Suk ;
ETRI Journal, volume 30, issue 4, 2008, Pages 600~602
A very small patch-type RFID tag antenna (UHF band) using ceramic material mountable on metallic surfaces is presented. The size of the proposed tag is 25 mm
3 mm. The impedance of the antenna can be easily matched to the tag chip impedance by adjusting the size of the shorting plate of the patch and the size of the feeding loop. The measured maximum reading distance of the tag at 910 MHz was 5 m when it was mounted on a 400 mm
400 mm metallic surface. The proposed design is verified by simulation and measurements which show good agreement.
A Switchable Microstrip Patch Antenna for Dual Frequency Operation
Sung, Young-Je ;
ETRI Journal, volume 30, issue 4, 2008, Pages 603~605
A novel design for equilateral-triangular microstrip antennas with switchable resonant frequency is proposed. For dual-frequency operation, the proposed design is achieved by loading a pair of slits in the triangular patch, and two PIN diodes are utilized to switch the slits on or off. By increasing the length of the slits, the lower resonant frequency can be varied in the range from 1.22 GHz to 1.72 GHz whereas the upper resonant frequency remains unchanged.
Clipping Prevention Scheme for MPEG Surround
Pang, Hee-Suk ;
ETRI Journal, volume 30, issue 4, 2008, Pages 606~608
MPEG Surround has a potential clipping problem since its encoding is based on downmixing a multichannel signal. We propose a clipping prevention scheme for MPEG Surround, which is composed of modification and recovery processes of a downmix signal with recovery information conveyed in arbitrary downmix gains of an MPEG Surround bitstream. Experiments show that the proposed scheme effectively prevents sound quality degradation caused by clipping problems with negligible additional bit rates.
Outage Probability of Opportunistic Amplify-and-Forward Relaying in Nakagami-m Fading Channels
Yang, Qinghai ; Zhong, Yingji ; Kwak, Kyung-Sup ; Fu, Fenglin ;
ETRI Journal, volume 30, issue 4, 2008, Pages 609~611
We address the outage performance for the opportunistic amplify-and-forward relaying strategies under Nakagami-m fading channels. A closed-form expression for the outage probability is derived. Simulation results verify our theoretical solutions.
A 6 Gbps/pin Low-Power Half-Duplex Active Cross-Coupled LVDS Transceiver with Switched Termination
Kim, Su-A ; Kong, Bai-Sun ; Lee, Chil-Gee ; Kim, Chang-Hyun ; Jun, Young-Hyun ;
ETRI Journal, volume 30, issue 4, 2008, Pages 612~614
A novel linear switched termination active cross-coupled low-voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross-coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared pre-amplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak-to-peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.
Novel Quasi-Elliptic Function Bandpass Filter Using Hexagonal Resonators with Capacitive Loading
Wang, Changtao ; Li, Wenming ; Liu, Feng ; Liu, Haiwen ;
ETRI Journal, volume 30, issue 4, 2008, Pages 615~617
A novel and compact elliptic-function bandpass filter is proposed in this letter. The techniques of slot etching and the addition of open stubs are applied to enhance the self-inductance and self-capacitance of hexagonal open-loop resonators. Thus, size reduction and improved transmission performance are obtained. Compared to the performance of the conventional design, the central frequency and insertion loss are reduced by 28% and 3.1 dB, respectively. Measurements show that the proposed filter has a fraction bandwidth of 23% at the central frequency of 1.84 GHz, and its insertion loss in the passband is less than -1.5 dB. The bandpass filter occupies only 12 mm
21.2 mm (approximately
An Efficient Load Balancing Mechanism in Distributed Virtual Environments
Jang, Su-Min ; Yoo, Jae-Soo ;
ETRI Journal, volume 30, issue 4, 2008, Pages 618~620
A distributed virtual environment (DVE) allows multiple geographically distributed objects to interact concurrently in a shared virtual space. Most DVE applications use a non-replicated server architecture, which dynamically partitions a virtual space. An important issue in this system is effective scalability as the number of users increases. However, it is hard to provide suitable load balancing because of the unpredictable movements of users and hot-spot locations. Therefore, we propose a mechanism for sharing roles and separating service regions. The proposed mechanism reduces unnecessary partitions of short duration and supports efficient load balancing.
Design and Implementation of a Multimodal Input Device Using a Web Camera
Na, Jong-Whoa ; Choi, Won-Suk ; Lee, Dong-Woo ;
ETRI Journal, volume 30, issue 4, 2008, Pages 621~623
We propose a novel input pointing device called the multimodal mouse (MM) which uses two modalities: face recognition and speech recognition. From an analysis of Microsoft Office workloads, we find that 80% of Microsoft Office Specialist test tasks are compound tasks using both the keyboard and the mouse together. When we use the optical mouse (OM), operation is quick, but it requires a hand exchange delay between the keyboard and the mouse. This takes up a significant amount of the total execution time. The MM operates more slowly than the OM, but it does not consume any hand exchange time. As a result, the MM shows better performance than the OM in many cases.
Adopting the Banked Register File Scheme for Better Performance and Less Leakage
Jang, Hyung-Beom ; Chung, Eui-Young ; Chung, Sung-Woo ;
ETRI Journal, volume 30, issue 4, 2008, Pages 624~626
Excessively high temperature deteriorates the reliability and increases the leakage power consumption of microprocessors. The register file, known as one of the hottest functional units in microprocessors, incurs frequent dynamic thermal management operations for thermal control. In this letter, we adopt the banked register file scheme, which was originally proposed to reduce dynamic power consumption. By simply modifying the register file structure, the temperature in the register file was reduced dramatically, resulting in 13.37% performance improvement and 10.49% total processor leakage reduction.