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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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The KIPS Transactions:PartA
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Korea Information Processing Society
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Volume & Issues
Volume 11A, Issue 7 - Dec 2004
Volume 11A, Issue 6 - Oct 2004
Volume 11A, Issue 5 - Oct 2004
Volume 11A, Issue 4 - Aug 2004
Volume 11A, Issue 3 - Jun 2004
Volume 11A, Issue 2 - Apr 2004
Volume 11A, Issue 1 - Feb 2004
Volume 11, Issue 2 - 00 2004
Volume 11, Issue 1 - 00 2004
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A Design of Cellular Array Parallel Multiplier on Finite Fields GF(
The KIPS Transactions:PartA, volume 11, issue 1, 2004, Pages 1~1
A cellular array parallel multiplier with parallel-inputs and parallel-outputs for performing the multiplication of two polynomials in the finite fields GF(
) is presented in this paper. The presented cellular array parallel multiplier consists of three operation parts: the multiplicative operation part (MULOP), the irreducible polynomial operation part (IPOP), and the modular operation part (MODOP). The MULOP and the MODOP are composed if the basic cells which are designed with AND Bates and XOR Bates. The IPOP is constructed by XOR gates and D flip-flops. This multiplier is simulated by clock period l㎲ using PSpice. The proposed multiplier is designed by 24 AND gates, 32 XOR gates and 4 D flip-flops when degree m is 4. In case of using AOP irreducible polynomial, this multiplier requires 24 AND gates and XOR gates respectively. and not use D flip-flop. The operating time of MULOP in the presented multiplier requires one unit time(clock time), and the operating time of MODOP using IPOP requires m unit times(clock times). Therefore total operating time is m+1 unit times(clock times). The cellular array parallel multiplier is simple and regular for the wire routing and have the properties of concurrency and modularity. Also, it is expansible for the multiplication of two polynomials in the finite fields with very large m.
A Cache Managing Strategy for Fast Media Data Access
문현주 ; 김석일 ;
The KIPS Transactions:PartA, volume 11, issue 1, 2004, Pages 11~11
Multimedia data processing in streaming pattern contains high spatial locality and low temporal locality. This paper has proposed a dynamic data prefetching scheme that fully exploits the regularity between memory addresses referred consecutively. Compared to the existing data prefetching scheme, the proposed scheme can reduce data Prefetching error when an application divides an way into smaller blocks and processes them block by block. Experimental results on various media benchmark programs show the proposed scheme predicts memory addresses more accurately and results in better performance than existing prefetching schemes.
Residential Gateway Design under Realtime Linux Environment
심장섭 ; 김종겸 ; 정순기 ;
The KIPS Transactions:PartA, volume 11, issue 1, 2004, Pages 21~21
In this paper, we describe the study of residential gateway design and the implementation of its core functional features under the realtime linux environment. This Paper has also suggested the developing example of device driver that can execute the realtime linux with stability based on the recent research findings of which is related to the functions of existing realtime operating system for residential gateway, and explained methods that can further improve performance by analyzing the performance characteristics of the system. And as a result, it was able to suggest the possibility of effective implementation of residential gateway under the realtime linux environment in this paper.
Development of A Web-cache System with Compression Capability
박진원 ; 김명균 ; 홍윤환 ;
The KIPS Transactions:PartA, volume 11, issue 1, 2004, Pages 29~29
As the number of Internet users and the amount of web contents have increased very fast, reducing the load of web servers and providing web services more rapidly have been great issues. A web-cache system, which is located between the user and the web server, has been used by many web service providers as an effective way to reduce the load of web servers and the web service response time. In this paper, we have developed a web-cache system which is based on the Squid cache and has a compression capability. The web-cache system in which compression capability reduces the amount of network traffic and the web service response time by transfering the web contents in the compressed format over the network between the web-cache system and the user. The performance enhancement is greater in the reverse-cache system than in the forward-cache system because in the case of the reverse-cache system, the cache reduces the amount of traffic on the Internet which is the bottleneck in the network path between the user and the web server. The experimentation result shows that the amount of data traffic has reduced from 2 to 8 times depending on the size of the web contents. The web server response time has reduced 37% on the average and when the size of the web content is greater than 10Kbyte, the response time has reduced 87% on the average.
An Integrated Development Environment for SyncML Server Applications
이지연 ; 최훈 ;
The KIPS Transactions:PartA, volume 11, issue 1, 2004, Pages 37~37
The SyncML, the standard synchronization protocol, supports the synchronization of various application services between a client and a server such as an address book, a calendar. Even with this standard protocol, SyncML application developers usually spend a long time and efforts implementing service specific logics and databases. This paper designed and implemented the SDE(Service Development Environment) which is an integrated development environment for SyncML server developers to develop an application service rapidly and correctly. The SDE consists of two components i.e., the Sync Library and the SEG(Sync Engine Generator) tool. To prove the applicability of this study we implemented a SyncML server by using the SDE and also carried out the correctness tests and the performance test. We hope this system helps developers implement mobile application services more efficiently.
An efficient interconnection network topology in dual-link CC-NUMA systems
The KIPS Transactions:PartA, volume 11, issue 1, 2004, Pages 49~49
The performance of the multiprocessor systems is limited by the several factors. The system performance is affected by the processor speed, memory delay, and interconnection network bandwidth/latency. By the evolution of semiconductor technology, off the shelf microprocessor speed breaks beyond G㎐, and the processors can be scalable up to multiprocessor system by connecting through the interconnection networks. In this situation, the system performances are bound by the latencies and the bandwidth of the interconnection networks. SCI, Myrinet, and Gigabit Ethernet are widely adopted as a high-speed interconnection network links for the high performance cluster systems. Performance improvement of the interconnection network can be achieved by the bandwidth extension and the latency minimization. Speed up of the operation clock speed is a simple way to accomplish the bandwidth and latency betterment, while its physical distance makes the difficulties to attain the high frequency clock. Hence the system performance and scalability suffered from the interconnection network limitation. Duplicating the link of the interconnection network is one of the solutions to resolve the bottleneck of the scalable systems. Dual-ring SCI link structure is an example of the interconnection network improvement. In this paper, I propose a network topology and a transaction path algorism, which optimize the latency and the efficiency under the duplicated links. By the simulation results, the proposed structure shows 1.05 to 1.11 times better latency, and exhibits 1.42 to 2.1 times faster execution compared to the dual ring systems.
Design and Implementation of UPnP-to-Jini Service
한상숙 ; 은성배 ; 김철민 ;
The KIPS Transactions:PartA, volume 11, issue 1, 2004, Pages 57~57
According to the development of home-network, home-network middleware supporting interoperability between devices connecting to home-network has been variously Proposed. As a typical middleware, UPnP and Jini are developed individually. So, to extend the usage of home-network, it is necessary to have connections among various home-network middleware. In this paper, we study about home-network middleware UPnP and Jini, and design and implement UPnP-to-Jini service which allows Jini client to use UPnP device using the speciality of UPnP performance process. Using application of light on-off we implemented the connection of them.
A Synchronous/Asynchronous Hybrid Parallel Power Iteration for Large Eigenvalue Problems by the MPMD Methodology
The KIPS Transactions:PartA, volume 11, issue 1, 2004, Pages 67~67
Most of today's parallel numerical schemes use synchronous algorithms, where some processors that have finished their tasks earlier than others must wait at synchronization points for correct computation. Hence overall performance of the system is dependent upon the speed of the slowest processor. In this paper, we devise a synchronous/asynchronous hybrid algorithm to accelerate convergence of the solution for finding the dominant eigenpair of a large matrix, by reducing the idle times of faster processors using MPMD programming methodology.
Formalized Web-based Data Searching System for GRID Environment
이상근 ; 황석찬 ; 최재영 ; 노경태 ;
The KIPS Transactions:PartA, volume 11, issue 1, 2004, Pages 75~75
To interact database data with GRID system, implementation and installation of data manipulation module which manipulates database data and its index is required. Developing a search system searching data on web-based database, and integrating it with grid system, it is possible that searching data on web and use it directly on GRID system without independent data module. So, we can build easy and effective grid system, and the system could have more flexible architecture adapting data change. In this paper, we propose a searching system which interacting web-based database with GRID systems. We integrated the searching system with a bio grid system which runs virtual screening jobs. As a result, UB Grid (Universal Bio Grid) is constructed. Developer could reduce time and effort required to integrate web data to GRID system, and user could use UB Grid system easily and effectively.
The Design and Implementation of Outer Encoder/Decoder for Terrestrial DMB
원지연 ; 이재흥 ; 김건 ;
The KIPS Transactions:PartA, volume 11, issue 1, 2004, Pages 81~81
In this paper, we designed the outer encoder/decoder for the terrestrial DMB that is an advanced digital broadcasting standard, implemented, and verified by using ALTERA FPGA. In the encoder part, it was created the parity bytes (16 bytes) from the input packet (188byte) of MPEG-2 TS and the encoded data was distributed output by the convolutional interleaver for Preventing burst errors. In the decoder part, It was proposed the algorithm that detects synchronous character suitable to DMB in transmitted data from the encoder. The circuit complexity in RS decoder was reduced by applying a modified Euclid's algorithm. This system has a capability to correct error of the maximum 8 bytes in a packet. After the outer encoder/decoder algorithm was verified by using C language, described in VHDL and implemented in the ALTERA FPGA chips.
Taxonomy of Abstraction
The KIPS Transactions:PartA, volume 11, issue 1, 2004, Pages 89~89
Abstraction is an important concept applied widely to variables, functions, complex data, abstract data types, classes and polymorphism in programming languages. However, the concept of abstraction has been considered as ambiguous and explained differently because it is not defined clearly and uniformly. In this paper, we analyse many aspects of abstraction in programming languages, and propose the taxonomy of abstraction. We classify abstraction according to the mechanism of formation into 4 categories such as mapping abstraction, bundling abstraction. integrating abstraction and extending abstraction. We also consider many concepts related closely to abstraction such as functions, abstract data types, objects, encapsulation and classes in the view of abstraction. These analysis and consideration will make it possible to explain uniformly various aspects of abstraction which have been treated individually and differently, and to understand the meanings, necessity and importance of abstraction more intensively.
Design of an Algorithmic Debugging Technique for Java Language
고훈준 ; 유원희 ;
The KIPS Transactions:PartA, volume 11, issue 1, 2004, Pages 97~97
This paper proposes to use an algorithmic debugging technique for locating logical errors in Java programs. The algorithmic debugging is a semi-automated debugging technique that builds an execution tree from a source program and locates logical errors, if any, included in the program from the execution tree with top-down method. So, it is very important to build a suitable execution tree from the various programming languages. In this paper we propose the method for building an execution tree iron Java programs and walk through an example. This approach could reduce the number of interactions between a user and a debugging system than the traditional step-wise debugging technique.