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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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The KIPS Transactions:PartA
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Korea Information Processing Society
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Volume & Issues
Volume 18A, Issue 6 - Dec 2011
Volume 18A, Issue 5 - Oct 2011
Volume 18A, Issue 4 - Aug 2011
Volume 18A, Issue 3 - Jun 2011
Volume 18A, Issue 2 - Apr 2011
Volume 18A, Issue 1 - Feb 2011
Selecting the target year
Hamiltonian Paths in Restricted Hypercube-Like Graphs with Edge Faults
Kim, Sook-Yeon ; Chun, Byung-Tae ;
The KIPS Transactions:PartA, volume 18A, issue 6, 2011, Pages 225~232
DOI : 10.3745/KIPSTA.2011.18A.6.225
Restricted Hypercube-Like (RHL) graphs are a graph class that widely includes useful interconnection networks such as crossed cube, Mobius cube, Mcube, twisted cube, locally twisted cube, multiply twisted cube, and generalized twisted cube. In this paper, we show that for an m-dimensional RHL graph G,
, with an arbitrary faulty edge set
has a hamiltonian path between any distinct two nodes s and t if dist(s, V(F))
or dist(t, V(F))
is the graph G whose faulty edges are removed. Set V(F) is the end vertex set of the edges in F and dist(v, V(F)) is the minimum distance between vertex v and the vertices in V(F).
Implementation of the L-SNS System based on Media Literacy as an Information Ethics Education Methodology
Lee, Myung-Suk ; Son, Yoo-Ek ;
The KIPS Transactions:PartA, volume 18A, issue 6, 2011, Pages 233~240
DOI : 10.3745/KIPSTA.2011.18A.6.233
In this paper, we design and implement an L-SNS system to reduce ever-increasing adverse effects of the Internet through the strengths of social network service system based on media literacy, including critical comprehension, creative expression, participation, communication ability, etc. The L-SNS system we proposed here was used the Smartphone as a medium of communication for learners, and to let them have indirect experience and real-time interaction. In addition, it provides the environment to make objective decisions through the process examining an in-depth discussion among other learners in the aspect of a third party.
Design and Implementation of the Differential Contents Organization System based on Each Learner's Level
Heo, Sun-Young ; Kim, Eun-Gyung ;
The KIPS Transactions:PartA, volume 18A, issue 6, 2011, Pages 241~248
DOI : 10.3745/KIPSTA.2011.18A.6.241
Many learning systems are applying Self-Directed Learning to improve learning efficiency. The degree of understanding of the same learning contents can be different even if the learner's level is same. Therefore, it is difficult to represent an effective learning experience because the learning is progressed by the determined difficulty of learning and the learning process even thought the provided content is difficult to understand. In this paper, we augmented SCORM to reconstruct the learning contents which are suitable for the changed level of each learner in real-time. Also, we designed and implemented this augmented SCORM based DCOS(Differential Contents Organization System). In order to provide the suitable contents for each learner, DCOS reorganizes learning contents based on the learner's level, the learner's achievement of learning objectives, and the correlation between learning objects, that is the component of the learning content. Each 30 Each 30 students studied e-learning contents, which are constructed based on the existing System and DCOS respectively. And the average score and system's satisfaction of the students who studied DCOS based e-learning contents was higher.
Design of Luma and Chroma Sub-pixel Interpolator for H.264 Motion Estimation
Lee, Seon-Young ; Cho, Kyeong-Soon ;
The KIPS Transactions:PartA, volume 18A, issue 6, 2011, Pages 249~254
DOI : 10.3745/KIPSTA.2011.18A.6.249
This paper describes an efficient design of the interpolation circuit to generate the luma and chroma sub-pixels for H.264 motion estimation. The circuit based on the proposed architecture does not require any input data buffering and processes the horizontal, vertical and diagonal sub-pixel interpolations in parallel. The performance of the circuit is further improved by simultaneously processing the 1/2-pixel and 1/4-pixel interpolations for luma components and the 1/8-pixel interpolations for chroma components. In order to reduce the circuit size, we store the intermediate data required to process all the interpolations in parallel in the internal SRAM's instead of registers. We described the proposed circuit at register transfer level and verified its operation on FPGA board. We also synthesized the gate-level circuit using 130nm CMOS standard cell library. It consists of 20,674 gates and has the maximum operating frequency of 244MHz. The total number of SPSRAM bits used in our circuit is 3,232. The size of our circuit (including logic gates and SRAM's) is smaller than others and the performance is still comparable to them.
Design and Implementation of Preemptive EDF Scheduling Algorithm in TinyOS
Yoo, Jong-Sun ; Kim, Byung-Kon ; Choi, Byoung-Kyu ; Heu, Shin ;
The KIPS Transactions:PartA, volume 18A, issue 6, 2011, Pages 255~264
DOI : 10.3745/KIPSTA.2011.18A.6.255
A sensor network is a special network that makes physical data sensed by sensor nodes and manages the data. The sensor network is a technology that can apply to many parts of field. It is very important to transmit the data to a user at real-time. The core of the sensor network is a sensor node and small operating system that works in the node. TinyOS developed by UC Berkeley is a sensor network operating system that used many parts of field. It is event-driven and component-based operating system. Basically, it uses non-preemptive scheduler. If an urgent task needs to be executed right away while another task is running, the urgent one must wait until another one is finished. Because of that property, it is hard to guarantee real-time requirement in TinyOS. According to recent study, Priority Level Scheduler, which can let one task preempt another task, was proposed in order to have fast response in TinyOS. It has restrictively 5 priorities, so a higher priority task can preempt a lower priority task. Therefore, this paper suggests Preemptive EDF(Earliest Deadline First) Scheduler that guarantees a real-time requirement and reduces average respond time of user tasks in TinyOS.
Pair Register Allocation Algorithm for 16-bit Instruction Set Architecture (ISA) Processor
Lee, Ho-Kyoon ; Kim, Seon-Wook ; Han, Young-Sun ;
The KIPS Transactions:PartA, volume 18A, issue 6, 2011, Pages 265~270
DOI : 10.3745/KIPSTA.2011.18A.6.265
Even though 32-bit ISA based microprocessors are widely used more and more, 16-bit ISA based processors are still being frequently employed for embedded systems. Intel 8086, 80286, Motorola 68000, and ADChips AE32000 are the representatives of the 16-bit ISA based processors. However, due to less expressiveness of the 16-bit ISA from its narrow bit width, we need to execute more 16-bit instructions for the same implementation compared to 32-bit instructions. Because the number of executed instructions is a very important factor in performance, we have to resolve the problem by improving the expressiveness of the 16-bit ISA. In this paper, we propose a new pair register allocation algorithm to enhance an original graph-coloring based register allocation algorithm. Also, we explain about both the performance result and further research directions.
Architectural Refactoring of Real-Time Software Design for Predictable Controls of Artificial Heart
Jeong, Se-Hun ; Kim, Hee-Jin ; Park, Sang-Soo ; Cha, Sung-Deok ;
The KIPS Transactions:PartA, volume 18A, issue 6, 2011, Pages 271~280
DOI : 10.3745/KIPSTA.2011.18A.6.271
Time-Triggered Architecture (TTA), one of real-time software design paradigms which executes tasks in timely manner, has long been advocated as being better suited in fore-sighting system behavior than event-triggered architecture (ETA). To gain this valuable feature of TTA, however, precise task designing process is mandatory. Alternatively, ETA tries to execute tasks whenever paired events are occurred. It provides intuitive and flexible basement to add/remove tasks and, moreover, better response time performance. However ETA is difficult to analyze because system behavior might be different depending on the order of interrupts detected by the system. Many previous researches recommended TTA when developing safety-critical real-time systems, but cost problem of task designing process and insufficient consensus for applying rigorous software engineering practice are still challenging in practice. This paper describes software refactoring process which applying TTA approach into ETA based embedded software in artificial heart system. We implemented dedicated interrupt monitoring program to capture existing tasks' real-time characteristics. Based on the captured information, proper task designing process is done. Real-time analysis using RMA (Rate-Monotonic Analysis) verified that new design guarantees timeliness of the system. Empirical experiments revealed that revised design is as efficient, when measured in terms of system's external output, as the old design and enhances predictability of the system behavior as well.
A study on the Design and Implementation of Simulator adapted in AMI Network environment
Yang, Il-Kwon ; Jung, Nam-Joon ; Lee, Sang-Ho ;
The KIPS Transactions:PartA, volume 18A, issue 6, 2011, Pages 281~292
DOI : 10.3745/KIPSTA.2011.18A.6.281
In this paper, a simulator adapted in AMI network environment with NS-2 was designed and implemented. The limited AMI operation environment such as processing times of data, network protocol and system performance can be simulated to find out the optimal AMI formations. Consequently, it is simulated under conditions that are closely analogous to the actual networks and each device. In future, the result of simulation would be applied to AMI network, mitigated the waste of resources and much contributed towards the real optimal AMI deployments in utilities.