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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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Journal of IKEEE
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Journal DOI :
Institude of Korean Electrical and Electronics Engineers
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Volume & Issues
Volume 14, Issue 4 - Dec 2010
Volume 14, Issue 3 - Sep 2010
Volume 14, Issue 2 - Jul 2010
Volume 14, Issue 1 - Apr 2010
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A Design of DisplayPort AUX Channel
Cha, Seong-Bok ; Yoon, Kwang-Hee ; Kim, Tae-Ho ; Kang, Jin-Ku ;
Journal of IKEEE, volume 14, issue 1, 2010, Pages 1~7
This paper presents an implementation of the DisplayPort AUX(Auxiliary) Channel. DisplayPort uses Main link, AUX Channel and Hot Plug Detect line to transfer the video & audio data. For isochronous transport service, source device converts to image and audio data which are to be transported through the Main Link and transports the restructured image and audio data to sink device. The AUX Channel provides link service and device service for discovering, initializing and maintaining the Main link. Hot Plug Detect line is used to confirm the connection between source device and sink device. The AUX Channel is implemented with 3315 LUTs(Look Up Table), 1466 Flip Flops and 168.782MHz max speed synthesized using Xilinx ISE 9.2i at SoC Master3.
Differential Capacitor-Coupled Successive Approximation ADC
Yang, Soo-Yeol ; Mo, Hyun-Sun ; Kim, Dae-Jeong ;
Journal of IKEEE, volume 14, issue 1, 2010, Pages 8~16
This paper presents a design of the successive approximation ADC(SA-ADC) applicable to a midium-low speed analog-front end(AFE) for the maximum 15MS/s CCD image processing. SA-ADC is effective in applications ranging widely between low and mid data rates due to the large power scaling effect on the operating frequency variations in some other way of pipelined ADCs. The proposed design exhibits some distinctive features. The "differential capacitor-coupling scheme" segregates the input sampling behavior from the sub-DAC incorporating the differential input and the sub-DAC output, which prominently reduces the loading throughout the signal path. Determining the MSB(sign bit) from the held input data in advance of the data conversion period, a kind of the signed successive approximation, leads to the reduction of the sub-DAC hardware overhead by 1 bit and the conversion period by 1 cycle. Characterizing the proposed design in a 3.3 V
CMOS process by Spectre simulations verified its validity of the application to CCD analog front-ends.
Calorie Expenditure Prediction Model of Elderly Living Alone using Motion Sensors for LBS Applications
Jung, Kyung-Kwon ; Kim, Yong-Joong ;
Journal of IKEEE, volume 14, issue 1, 2010, Pages 17~24
This paper presents calorie expenditure prediction model of daily activity of elderly living alone for LBS(Location Based Service) applications. The proposed method is to describe the daily activity patterns of older adult using PIR (Passive InfraRed) motion sensors and to examine the relationships between physical activity and calorie expenditure. The developed motion detecting system is composed of a sensing system and a server system. The motion detecting system is a set of wireless sensor nodes which has PIR sensor to detect a motion of elder. Each sensing node sends its detection signal to a home gateway via wireless link. The home gateway stores the received signals into a remote database. The server system is composed of a database server and a web server, which provides web-based monitoring system to caregivers for more effective services. The experiment results show the adaptability and feasibility of the calorie expenditure model.
Location error analysis of a real time locating system in a multipath environment
Myong, Seung-Il ; Mo, Sang-Hyun ; Lee, Heyung-Sub ; Park, Hyung-Rae ; Seo, Dong-Sun ;
Journal of IKEEE, volume 14, issue 1, 2010, Pages 25~32
In this paper, we analyze the location accuracy of real-time locating systems (RTLS) in multipath environments, where the RTLS complies with an ISO/IEC 24730-2 international standard. RTLS readers should have an ability not only to recover the transmitted signal but also provide arrival timing information from the received signal. In the multipath environments, in general, the transmitted signal goes through both direct and indirect paths, and then it becomes some distorted form of the transmitted signal. Such multipath components have a critical effect on deciding the first arrival timing of the received signal. To analyze the location error of the RTLS in the multipath environments, we assume two multipath components without considering an additive white Gaussian noise. Through the simulation and real test results, we confirm that the location error does not occur when the time difference between two paths is more than 1.125Tc, but the location error of about 2.4m happens in case of less than 0.5Tc. In particular, we see that the resolvability of two different paths depends largely on the phase difference for the time difference of less than 1Tc.
A 5-Gb/s Continuous-Time Adaptive Equalizer
Kim, Tae-Ho ; Kim, Sang-Ho ; Kang, Jin-Ku ;
Journal of IKEEE, volume 14, issue 1, 2010, Pages 33~39
In this paper, a 5Gb/s receiver with an adaptive equalizer for serial link interfaces is proposed. For effective gain control, a least-mean-square (LMS) algorithm was implemented with two internal signals of slicers instead of output node of an equalizing filter. The scheme does not affect on a bandwidth of the equalizing filter. It also can be implemented without passive filter and it saves chip area and power consumption since two internal signals of slicers have a similar DC magnitude. The proposed adaptive equalizer can compensate up to 25dB and operate in various environments, which are 15m shield-twisted pair (STP) cable for DisplayPort and FR-4 traces for backplane. This work is implemented in
1-poly 4-metal CMOS technology and occupies
. Measurement results show only 6mW small power consumption and 2Gbps operating range with fabricated chip. The equalizer is expected to satisfy up to 5Gbps operating range if stable varactor(RF) is supported by foundry process.
A 2.7Gbps & 1.62Gbps Dual-Mode Clock and Data Recovery for DisplayPort in
Lee, Seung-Won ; Kim, Tae-Ho ; Lee, Suk-Won ; Kang, Jin-Ku ;
Journal of IKEEE, volume 14, issue 1, 2010, Pages 40~46
This paper describes a clock and data recovery (CDR) circuit that supports dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a "Mode" switch control. The chip has been implemented using
CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of 37ps(@2.7Gbps) and 27ps(@1.62Gbps) in the recovered data. The power dissipation is 80mW at 2.7Gbps rate from a 1.8V supply.
A Study on the Performance of Noise Reduction using Multi-Microphones for Digital Hearing Aids
Kang, Hyun-Deok ; Song, Young-Rok ; Lee, Sang-Min ;
Journal of IKEEE, volume 14, issue 1, 2010, Pages 47~54
In this study, we analyzed the reduction of noise in a noise environment using 2, 3, 4 or 5 microphones in digital hearing aids. In order to be able to use this in actual digital hearing aids, we made the experiment microphone set similar to the behind-the-ear type (BTE) and then recorded the signal accordingly, with each situation. With the recorded signals, we reduced the noise in each signal by a noise reduction algorithm using multi-microphones. As a result, in the case of By comparing the SNR (Signal to Noise Ratio) and PESQ (Perceptual Evaluation of Speech) measurements, before and after the noise reduction, the results showed that the improvement in performance was highest when three or four microphones were used. Generally, when two or more microphones were used, we found that as the number of microphones increased there was an increase in performance.
Analysis of the electrical characteristics of the novel TIGBT with additional pMOS
Lee, Hyun-Duck ; Won, Jong-Il ; Yang, Yil-Suk ; Koo, Yong-Seo ;
Journal of IKEEE, volume 14, issue 1, 2010, Pages 55~64
In this paper, we proposed the novel TIGBT with an additional p-type MOS structure to achieve the improved trade-off between turn-off and on-state voltage drop(Vce(sat)). These low on-resistance and the fast switching characteristics of the proposed TIGBT are caused by an enhanced electron current injection efficiency which is caused by additional p-type MOS structure. In the simulation result, the proposed TIGBT has the lower on state voltage of 1.67V and the shorter turn-off time of 3.1us than those of the conventional TIGBT(2.25V, 3.4us).
A CMOS Fractional-N Frequency Synthesizer for DTV Tuners
Ko, Seung-O ; Seo, Hee-Teak ; Park, Jong-Tae ; Yu, Chong-Gun ;
Journal of IKEEE, volume 14, issue 1, 2010, Pages 65~74
The Digital TV(DTV) standard has ushered in a new era in TV broadcasting and raised a great demand for DTV tuners. There are many challenges in designing a DTV tuner, of which the most difficult part is the frequency synthesizer. This paper presents the design of a frequency synthesizer for DTV Tuners in a
CMOS process. It satisfies the DTV(ATSC) frequency band(54~806MHz). A scheme is proposed to cover the full band using only one VCO. The VCO has been designed to operate at 1.6~3.6GHz band such that the LO pulling effect is minimized, and reliable broadband characteristics have been achieved by reducing the variations of VCO gain and frequency step. The simulation results show that the designed VCO has gains of 59~94MHz(
23%) and frequency steps of 26~42.5MHz(
24%), and a very wide tuning range of 76.9%. The designed frequency synthesizer has a phase noise of -106dBc/Hz at 100kHz offset, and the lock time is less than
sec. It consumes 20~23mA from a 1.8V supply, and the chip size including PADs is 2.0mm