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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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Journal of IKEEE
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Journal DOI :
Institude of Korean Electrical and Electronics Engineers
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Volume & Issues
Volume 16, Issue 4 - Dec 2012
Volume 16, Issue 3 - Sep 2012
Volume 16, Issue 2 - Jun 2012
Volume 16, Issue 1 - Mar 2012
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Trench Power MOSFET using Separate Gate Technique for Reducing Gate Charge
Cho, Doohyung ; Kim, Kwangsoo ;
Journal of IKEEE, volume 16, issue 4, 2012, Pages 283~289
DOI : 10.7471/ikeee.2012.16.4.283
In this paper, We proposed Separate Gate Technique(SGT) to improve the switching characteristics of Trench power MOSFET. Low gate-to-drain 전하 (Miller 전하 : Qgd) has to be achieved to improve the switching characteristics of Trench power MOSFET. A thin poly-silicon deposition is processed to form side wall which is used as gate and thus, it has thinner gate compared to the gate of conventional Trench MOSFET. The reduction of the overlapped area between the gate and the drain decreases the overlapped charge, and the performance of the proposed device is compared to the conventional Trench MOSFET using Silvaco T-CAD. Ciss(input capacitance : Cgs+Cgd), Coss(output capacitance : Cgd+Cds) and Crss(reverse recovery capacitance : Cgd) are reduced to 14.3%, 23% and 30% respectively. To confirm the reduction effect of capacitance, the characteristics of inverter circuit is comprised. Consequently, the reverse recovery time is reduced by 28%. The proposed device can be fabricated with convetional processes without any electrical property degradation compare to conventional device.
Quiet Zone Implementation for VHF Antenna Measurement in Semi-Anechoic Chamber
Moon, Jung-Ick ;
Journal of IKEEE, volume 16, issue 4, 2012, Pages 290~296
DOI : 10.7471/ikeee.2012.16.4.290
In this study, an effective echo-suppression and cancellation technique using reflectors in semi-anechoic chamber and time-domain measurement is proposed. By using the proposed technique, the uniformity of electric field in QZ(Quiet Zone) could be improved and the antenna test environments similar to the fully anechoic chamber could be accomplished. The performances of the proposed test environments is verified with the simulated and measured data. And it is demonstrated that this test environment is possible to use the measuring the radiational characteristics of a small antenna in VHF band.
Effective Design of the Broadband Horn Antenna Using Multi-mode Network Analysis
Moon, Jung-Ick ; Cho, In-Gui ; Kim, Sung-Min ;
Journal of IKEEE, volume 16, issue 4, 2012, Pages 297~303
DOI : 10.7471/ikeee.2012.16.4.297
This paper proposes the effective design procedure for a broadband, double-ridged horn antenna for evaluating the performance of the RF energy harvesting system with a multi-band rectenna. Using multi-mode network analysis, the higher-mode scattering parameters of the transition and horn were acquired and applied to the antenna design, respectively. As a result, the computing time could be reduced and the calculated VSWR(voltage standing wave ratio) of the antenna was very similar to the analyzed result using fully electromagnetic simulation. And there was also good agreement between the simulated and measured results. The designed broadband antenna has a bandwidth of 660~6360 MHz and 6~13.7 dBi peak radiation gain.
Implementation of Parallel Processing Interpolation Algorithm for Multicore GPU
Lee, Kwang-Yeob ; Kim, Chi-Yong ;
Journal of IKEEE, volume 16, issue 4, 2012, Pages 304~309
DOI : 10.7471/ikeee.2012.16.4.304
As resolution for displays is recently more and more increasing, the amount of data abd calculation that graphic hardware needs to process are also increasing. Especially the amount of data processing by rasterizer is rapidly increasing. This paper used an algorism using coordinates in center of gravity and area for triangle instead of using bilinear algorism used by conventional interpolation, which is to make it easier for parallel processing by rasterizer. This paper implemented designed rasterizer under FPGA environment, and compared it with conventional rasterizer and verified it. This rasterizer is proved to have approximately 50% higher performance compared to conventional one.
Method of Multi Thread Management based on Shader Instruction for Mobile GPGPU
Lee, Kwang-Yeob ; Park, Tae-Ryong ;
Journal of IKEEE, volume 16, issue 4, 2012, Pages 310~315
DOI : 10.7471/ikeee.2012.16.4.310
This thesis is intended to design multi thread mobile GPGPU optimized in mobile environment, and to verify an effective thread management method of the multi thread mobile processor. In thread management, there is no management hardware and implement with software instructions. For the verification of the multi thread management method, Lane detection algorithm was implemented to compare nVidia's CUDA Architecture and the designed GPGPU in terms of thread management efficiency. The number of thread is normalized to 48 threads. An implemented Land Detection Algorithm is composed of Gaussian filter algorithm and Sobel Edge Detection algorithm. As a result, the designed GPGPU's thread efficiency is up to 2 times higher than CUDA's thread efficiency.
An Energy-Efficient Deployment Strategy for Micro Base Station in Wireless Cellular Systems
Oh, Eunsung ;
Journal of IKEEE, volume 16, issue 4, 2012, Pages 316~321
DOI : 10.7471/ikeee.2012.16.4.316
In this paper, we study the energy-efficient deployment strategy for micro base station (BS) in wireless cellular systems. Firstly, we formulate a general problem pertaining to total energy consumption minimization with the requirement of area spectral efficiency (ASE). We start from an observation about the correlation between the area covered by an additional micro BS and the increment of ASE. Under such an observation, we propose an efficient greedy micro BS deployment algorithm. Simulations show that the proposed deployment algorithm can deploy micro BSs with a slight performance reduction comparing with the optimal solution.
Design of Digital PLL using Binary Phase-Frequency Detector and Counter for Digital Phase Detection
Han, Jong-Seok ; Yoon, Kwan ; Kang, Jin-Ku ;
Journal of IKEEE, volume 16, issue 4, 2012, Pages 322~327
DOI : 10.7471/ikeee.2012.16.4.322
In this paper, a digital phase-locked loop(Digital-PLL) circuit with a new phase-to-digital converter(P2D) is described. The proposed digital PLL is composed a P2D, a digital loop filter(DLF), and a digitally controlled oscillator(DCO). The P2D generates a digital code for a phase error. The proposed P2D used a binary phase frequency detector(BPFD) and a counter in place of a time-to-digital converter(TDC) for simple structure, compact area and low power consumption. The proposed circuit was designed with CMOS 0.18um process. The simulation shows the circuit operates with the 1.0 to 2.2GHz with the power consumption of 16.2mW at 1.65GHz and the circuit occupies the chip area of
Comparisons of RCS Characteristic of Spherical Frequency Selective Surfaces with FSS Element Arrangement
Hong, Ic-Pyo ; Lee, In-Gon ;
Journal of IKEEE, volume 16, issue 4, 2012, Pages 328~334
DOI : 10.7471/ikeee.2012.16.4.328
In this paper, we analyzed the electromagnetic characteristics of the spherical frequency selective surface with different arrangement of crossed dipole slot elements for reducing the RCS(radar cross section). The three dimensional MOM(method of moment) with RWG basis is used to analyze the proposed structure. To reduce the simulation time, we applied the BiCGSTab(Biconjugate Gradient Stabilized) algorithm as an iterative method and presented the comparison results with Mie's theoretical results for PEC sphere to show the validity of this paper. From the simulation results, the different arrangement of elements array showed the difference RCS that cannot be negligible. The arrangement method of element in frequency selective surface will be one of variables for the design of curved frequency selective structures.
A Study on Step Up-Down AC-DC Converter with DCM-ZVS of High Performance
Kwak, Dong-Kurl ;
Journal of IKEEE, volume 16, issue 4, 2012, Pages 335~342
DOI : 10.7471/ikeee.2012.16.4.335
This paper is studied on a new DCM-ZVS step up-down AC-DC converter of high performance, that is, high system efficiency and power factor correction (PFC). The switching devices in the proposed converter are operated by soft switching technique using a new quasi-resonant circuit, and are driven with discontinuous conduction mode (DCM) according to pulse width modulation (PWM). The quasi-resonant circuit uses a step up-down inductor and a loss-less snubber capacitor. The proposed converter with DCM also simplifies the requirement of control circuits and reduces the number of control components. The input AC current waveform in the proposed converter becomes a quasi-sinusoidal waveform proportional to the magnitude of input AC voltage under constant switching frequency. As a result, the proposed converter obtains low switching power loss and high efficiency, and its input power factor is nearly in unity. The validity of the analytical findings is confirmed by some computer simulation results and experimental results.
Design of a Algorithmic ADC for Digital PFC Controller
Jang, Ki-Chang ; Kim, Jin-Yong ; Hwang, Sang-Hoon ; Choi, Joong-Ho ;
Journal of IKEEE, volume 16, issue 4, 2012, Pages 343~348
DOI : 10.7471/ikeee.2012.16.4.343
A 11b 100KS/s Algorithmic ADC for Digital PFC controller is proposed. The proposed Algorithmic ADC structure for 11bit resolution is based on a cyclic architecture to reduce chip area and power consumption. The prototype Algorithmic ADC implemented with a 0.18um 1Poly-3Metal CMOS process shows a SNDR 66.7dB and ENOB 10.78bits. And the current consumption is about 780uA at 100KS/s and 5V. The occupied active die area is
Efficient Real-time Lane Detection Algorithm Using V-ROI
Dajun, Ding ; Lee, Chanho ;
Journal of IKEEE, volume 16, issue 4, 2012, Pages 349~355
DOI : 10.7471/ikeee.2012.16.4.349
Information technology improves convenience, safety, and performance of automobiles. Recently, a lot of algorithms are studied to provide safety and environment information for driving, and lane detection algorithm is one of them. In this paper, we propose a lane detection algorithm that reduces the amount of calculation by reducing region of interest (ROI) after preprocessing. The proposed algorithm reduces the area of ROI a lot by determining the candidate regions near lane boundaries as V-ROI so that the amount of calculation is reduced. In addition, the amount of calculation can be maintained almost the same regardless of the resolutions of the input images by compressing the images since the lane detection algorithm does not require high resolution. The proposed algorithm is implemented using C++ and OpenCV library and is verified to work at 30 fps for realtime operation.
Fast algorithm for Traffic Sign Recognition
Dajun, Ding ; Lee, Chanho ;
Journal of IKEEE, volume 16, issue 4, 2012, Pages 356~363
DOI : 10.7471/ikeee.2012.16.4.356
Information technology improves convenience, safety, and performance of automobiles. Recently, a lot of algorithms are studied to provide safety and environment information for driving, and traffic sign recognition is one of them. It can provide important information for safety driving. In this paper, we propose a method for traffic sign detection and identification concentrating on reducing the computation time. First, potential traffic signs are segmented by color threshold, and a polygon approximation algorithm is used to detect appropriate polygons. The potential signs are compared with the template signs in the database using SURF and ORB feature matching method.
Generation of 10 GHz Short Pulses from Continuous Wave Laser Using Cascaded Intensity and Phase Modulators and a Single Mode Optical Fiber
Sung, Hyun-Ju ; Seo, Dong-Sun ;
Journal of IKEEE, volume 16, issue 4, 2012, Pages 364~368
DOI : 10.7471/ikeee.2012.16.4.364
We generate 10 GHz short pulses from a continuous wave laser at 1.5 um by cascaded intensity and phase modulation, followed by chirp compensation using a single mode fiber. The measured spectral and pulse widths are 0.64 nm and 5.7 ps respectively, resulting in the time-bandwidth product of 0.46.
Remote Image Control by Hand Motion Detection
Lim, Jung-Geun ; Han, Kyongho ;
Journal of IKEEE, volume 16, issue 4, 2012, Pages 369~374
DOI : 10.7471/ikeee.2012.16.4.369
This paper handles the UX implementation for system control using the visual input information of hand motion. Kinect sensor from Microsoft is used to acquire the user's skeleton image from the 3-D depth map at a rate of 30 frames per sec. and eventually knows the x-y coordinates of hand joints. The x-y coordinate value changes of hands between the present frame and next frame shows the direction of changes and rotation of changes and the various hand motion is used as a UX input command for remote image control on smart TV, etc. Through the experiments, we showed the implementation of the proposed idea.
An Efficient Face Detection Method using Skin Color Information and Parallel Processing in Multi-Core SoC
Kim, Hong-Hee ; Lee, Jae-Heung ;
Journal of IKEEE, volume 16, issue 4, 2012, Pages 375~381
DOI : 10.7471/ikeee.2012.16.4.375
In this paper, we present an implementation of Viola-Jones algorithm in a multi-core SoC by using skin color information and a parallel processing method. In order to reduce unnecessary operations and improve the detection speed, we adopted a face detection algorithm based on skin color and deleted background image. The algorithm is functionally divided into several parts taking account of the size and the dependency so that the divided functions can be proceeded in parallel. Experiment results in SoC with built-in Cortex-A9 multi core show that it is about 1.8 times faster than the existing algorithm which is not divided.
Acceleration Method of Inter Prediction using Advanced SIMD
Kim, Wan-Su ; Lee, Jae-Heung ;
Journal of IKEEE, volume 16, issue 4, 2012, Pages 382~388
DOI : 10.7471/ikeee.2012.16.4.382
An H.264/AVC fast motion estimation methodology is presented in this paper. Advanced SIMD based NEON which is one of the parallel processing methods is supported under the ARM Cortex-A9 dual-core platform. NEON is applied to a full search technique with one of the various motion estimation methods and SAD operation count of each macroblock is reduced to 1/4. Pixel values of the corresponding macroblock are assigned to eight 16-bit NEON registers and Intrinsic function in NEON architecture carried out 128 bits arithmetic operations at the same time. In this way, the exact motion vector with the minimum SAD value among the calculated SAD values can be designated. Experimental results show that performance gets improved 30% above average in accordance with the size of image and macroblock.
Software-based Encryption Pattern Bootstrap for Secure Execution Environment
Choi, Hwa-Soon ; Lee, Jae-Heung ;
Journal of IKEEE, volume 16, issue 4, 2012, Pages 389~394
DOI : 10.7471/ikeee.2012.16.4.389
Most current systems have ignored security vulnerability concerned with boot firmware. It is highly likely that boot firmware may cause serious system errors, such as hardware manipulations by malicious programs or code, the operating system corruption caused by malicious code and software piracy under a condition of no consideration of security mechanism because boot firmware has an authority over external devices as well as hardware controls. This paper proposed a structural security mechanism based on software equipped with encrypted bootstrap patterns different from pre-existing bootstrap methods in terms of securely loading an operating system, searching for malicious codes and preventing software piracy so as to provide reliability of boot firmware. Moreover, through experiments, it proved its superiority in detection capability and overhead ranging between 1.5 % ~ 3 % lower than other software security mechanisms.
Performance analysis of subjective Loudness meter with ITU-R BS. 1387-1 algorithm for digital audio
Ngan, Nguyen Vo Bao ; Park, Seonggyoon ; Ro, Soonghwan ; Han, Chankyu ;
Journal of IKEEE, volume 16, issue 4, 2012, Pages 395~404
DOI : 10.7471/ikeee.2012.16.4.395
In this paper, the perceived loudness metering algorithm based on ITU-R BS.1387-1 was investigated and implemented, and its performance was evaluated by applying to 23 pure tones and 9 digital audio samples. Error of the tone test results compared with ISO226:2003 was below 5%, and sample test results, in comparison with Moore's algorithm, showed deviation of less than 4.7% and correlation of 0.96. On the other hand, it was investigated how the implemented algorithm's performance was subject to auditory pitch scale. Its result showed that the algorithm with 37 auditory filters, through correcting a bias effect, has a good performance of less than 2% in comparison with the one with 109 auditory filters.
Design and Performance Evaluation of On-chip Antenna for Ultra Low Power Wireless Transceiver
Kwon, Won-Hyun ;
Journal of IKEEE, volume 16, issue 4, 2012, Pages 405~409
DOI : 10.7471/ikeee.2012.16.4.405
In this paper, on-chip antennas applicable to ultra low power wireless transceiver are designed and evaluated. Using
SiGe MMIC process, 4 types of antenna with
dimensions are fabricated. The on-wafer measurement in a microwave probe station is conducted to measure the input VSWR and antenna performance of the designed on-chip antenna. Performance evaluation results show that developed antennas can be easily integrated into one-chip RF transceiver for ubiquitous applications, including WPAN and human body communications.