Go to the main menu
Skip to content
Go to bottom
REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
Journal of IKEEE
Journal Basic Information
Journal DOI :
Institude of Korean Electrical and Electronics Engineers
Editor in Chief :
Volume & Issues
Volume 7, Issue 2 - Dec 2003
Volume 7, Issue 1 - Jul 2003
Selecting the target year
A Study on Network Load Management in MANET
Kang, Kyeong-In ; Bae, Park-Kyong ; Jung, Chan-Hyeok ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 127~134
Ad Hoc Networks, autonomous distributed network using routing scheme, does not operate properly owing to multi flow service when network load increases at specific network node. In this paper, we suggest traffic management routing protocol in Ad Hoc Network to reduce network traffic congestion and distribute network load in data transmission. Through test results of proposed algorithm under NS(Network Simulator)simulator environments . we acquired reduced network load and increased data transmission rate.
MVL Data Converters Using Neuron MOS Down Literal Circuit
Han, Sung-Il ; Na, Gi-Soo ; Choi, Young-Hee ; Kim, Heung-Soo ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 135~143
This paper describes the design techniques of the data converters for Multiple-Valued Logic(MVL). A 3.3V low power 4 digit CMOS analog to quaternary converter (AQC) and quaternary to analog converter (QAC) mainly designed with the neuron MOS down literal circuit block has been introduced. The neuron MOS down literal architecture allows the designed AQC and QAC to accept analog and 4 level voltage inputs, and enables the proposed circuits to have the multi-threshold properity. Low power consumption of the AQC and QAC are achieved by utilizing the proposed architecture.
A Unified Data Model for Conceptual Data Modeling
Nah, Yun-Mook ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 144~155
In this paper, a conceptual data model, called the UDM(Unified Data Model), to efficiently represent database structures related with object technology and complex structured data, is proposed. This model integrates major features of modern data models, such as E-R model, Semantic Object Model, and UML, especially from the viewpoint of database design. This model is basically a simplified, but extended version of the Object-Relationship Model, which was proposed to model complex structures of temporal-spatial multimedia data. This model incorporates some of the important semantic and structural information of modern database applications and it is designed to support all of the major logical database models, including relational, object-relational, object-oriented, and (semi-)structured databases. A special diagrammatic technique, called the UDD(Unified Data Diagram), is introduced as a tool for database design. Also, possible ways to derive logical views of data from this unified data model are presented. The proposed model can be utilized as a convenient and practical tool for conceptual database designs.
Adaptive Fuzzy Observer without SPR Condition for Uncertain Nonlinear Systems
Park, Jang-Hyun ; Kim, Seong-Hwan ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 156~165
This paper describes the design of a robust adaptive fuzzy observer for uncertain nonlinear dynamical system. We propose a new method in which no strictly positive real (SPR) condition is needed. No a priori knowledge of an upper bound on the lumped uncertainty is required. The Lyapunov synthesis approach is used to guarantee a semi-global uniform ultimate boundedness property of the state observation error, as well as of all other signals in the closed-loop system. The theoretical results are illustrated through a simulation example of a mass-spring-damper system.
A High-Level Data Path Allocation Algorithm for Low Power Architecture
Lin, Chi-Ho ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 166~171
In this paper, we propose a minimal power data path allocation algorithm for low power circuit design. The proposed algorithm minimizes switching activity for input variables in scheduled CDFG. Allocations are further divided into the tasks of register allocation and module allocation. The register allocation algorithm execute that it eliminate spurious switching activity in functional unit and minimize the numbers of multiplexer. Also, resource allocation method selects a sequence of operations for a module such that the switching activity is reduced. Therefore, the algorithm executes to minimize the switching activity of input values, sequence of operations and number of multiplexer. Experimental results using benchmarks show that power is reduction effect from 13% to 17% power consumption, when compared with the Genesis-lp high-level synthesis system.
A study on the design of thyristor-type ESD protection devices for RF IC's
Choi, Jin-Young ; Cho, Kyu-Sang ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 172~180
Based on simulation results and accompanying analysis, we suggest a thyristor-type ESD protection device structure suitable for implementation in standard CMOS processes to reduce the parasitic capacitances added to the input nodes, which is very important in CMOS RF ICs. We compare DC breakdown characteristics of the suggested device to those of a conventional NMOS protection device to show the benefits of using the suggested device for ESD protection. The characteristic improvements are demonstrated and the corresponding mechanisms are explained based on simulations. Structure dependencies are also examined to define the optimal structure. AC simulation results are introduced to estimate the magnitude of reduction in the added parasitic capacitance when using the suggested device for ESD protection. The analysis shows a possibility of reducing the added parasitic capacitance down to about 1/40 of that resulting with a conventional NMOS protection transistor, while maintaining robustness against ESD.
Priority Service Algorithm of Packet Switch for Improvement in QoS
Jung, Hae-Young ; Lee, Heung-Jae ; Choe, Jin-Kyu ; Lee, Kyou-Ho ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 181~187
In high speed packet switching network, packet service by priority scheme prefer to QoS. Efficient packet service according to the priority scheme in high speed packet switch is a key point. Therefore development of priority service algorithm in the packet switch is very important. In this paper, we proposed W-iSLIP algorithm that service time take queue length into consideration and compared the proposed W-iSLIP algorithm to other previous proposed algorithm through simulation. Simulation results show 2.6% performance elevation in average delay, and 34.6% performance elevation in priority service.
Development of software demultiplexer for DTV Signal Reception
Jin, Hyun-Joon ; Park, Nho-Kyung ; Kim, Moo-Han ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 188~196
In this paper, a demultiplexer for MPEG-2 Transport Stream which can be applied to terrestrial digital broadcast is developed. The demultiplexer separates video, audio, and data from MPEG-2 multimedia stream and transports them to each decoders respectively. While most existing demultiplexers of MPEG-2 transport stream have been developed as hardware systems, but the fast increment of computer's performance enables a software demultiplexer to be worked in realtime. The developed demultiplexer is implemented as a software module called a filter using DirectShow of Microsoft which is based on COM(Component Object Model)and works on the Windows system. The operation of the demultiplexer is verified by using the GraphEdit tool and rendering a test file formatted as MPEG-2 transport stream.
A Study on Simple chip Design that Convert Improved YUV signal to RGB signal
Lee, Chi-Woo ; Park, Sang-Bong ; Jin, Hyun-Jun ; Park, Nho-Kyung ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 197~209
A current TV out format is quite different from that of HDTV or PC monitor in encoding techniques. In other words, a conventional analog TV uses interlaced display while HDTV or PC monitor uses Non-interlaced / Progressive-scanned display. In order to encode image signals coming from devices that takes interlaced display format for progressive scanned display, a hardware logic in which scanning and interpolation algorithms are implemented is necessary. The ELA(Edge-Based Line Average) algorithm have been widely used because it provided good characteristics. In this study, the ADI(Adaptive De-interlacing Interpolation) algorithm using to improve the ELA algorithm which shows low quality in vertical edge detections and low efficiency of horizontal edge lines. With the De-interlacing ASIC chip that converts the interlaced Digital YUV to De-interlaced Digital RGB is designed. The VHDL is used for chip design.
A Novel Morphological Characteristic Value Extraction Method for Content-Based Image Retrieval
Eo, Jin-Woo ; Lee, Dong-Jin ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 210~217
A novel characteristic value extraction method based on mathematical morphology is proposed. Morphological spatial frequency defined by morphological pattern distribution function is introduced and applied to define a new feature called ‘average height.' The average height is used to define a characteristic value which is to be used to generate an index key value for content-based image retrieval. Superiority of the method was proved for various images by experiment. Furthermore the fact that the proposed method does not need threshold to obtain binary image provides its applicability to content-based image retrieval.
Optimization Analysis for Homogeneous Field Structure of GTEM-CELL
Kim, Jong-Seong ; Seo, Kang ; Jeong, Seong-IL ; Lee, Han-Young ; Lee, Jong-Arc ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 218~222
Even if using the standard field test which radiation of electric wave and measurement test equipment there are difficult thing that building test equipment. so, we can use the substitution test field. In this paper, for optimization analysis for homogeneous field structure of GTEM-CELL (Giga hertz Transverse Electro Magnetic Cell) that calculate electromagnetic field characteristic for variable of each structure and characteristic impedance inner conductor.
A study on the design of an Dual Inverted-F Internal Antenna for the WLAN`s Band
Kang, Jeong-Jin ; Kang, Seo ; Jeung, Seung-Il ; Kim, Wan-Sik ; Lee, Jong-Arc ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 223~229
In this thesis, the characteristics of an inverted-F antenna for the 2.4GHz and 5.8GHz zwirless local area network(WLAN) have been analysed in terms of the variation of design parameters. The antenna can be integrated on WLAN for notebook printed circuit board, and the characteristics in terms of the variation of the gap between feed line and shorting stub, gap between antenna's leg and ground plane, antenna leg's width, substrate's height and dielectric constant are analysed. By using these characterization plot of design parameter, the tuning techniques are proposed to design optimum antenna. The designed antenna has 170MHz, 500MHz frequency bandwidth ,VSWR is 1.6, 1.14 and 3.5dBi gain.
Ka-Band MMIC VCO Design and its Fabrication
Kim, Wan-Sik ; Kang, Seo ; Kang, Dae-Hyun ; Jeong, Seong-Il ; Lee, Jae-Cheul ; Lee, Jong-Arc ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 230~235
A small and integrated MMIC VCO(Voltage Controlled Oscillator) at Ka-band has been developed. This oscillator was designed as Clapp-Gouriet type scheme, fabricated, and implemented on the carrier. This was connected to an alumna substrate on the carrier providing output port for module, utilizing ribbon and wire bonding technique allowing the loss of 0.2dB. This VCO module showed the excellent performance.
Design of a CMOS Tx RF/IF Single Chip for PCS Band Applications
Moon, Yo-Sup ; Kwon, Duck-Ki ; Kim, Keo-Sung ; Park, Jong-Tae ; Yu, Chong-Gun ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 236~244
In this paper, RF and IF circuits for mobile terminals which have usually been implemented using expensive BiCMOS processes are designed using CMOS circuits, and a Tx CMOS RF/IF single chip for PCS applications is designed. The designed circuit consists of an IF block including an IF PLL frequency synthesizer, an IF mixer, and a VGA and an RF block including a SSB RF mixer and a driver amplifier, and performs all transmit signal processing functions required between digital baseband and the power amplifier. The phase noise level of the designed IF PLL frequency synthesizer is -114dBc/Hz@100kHz and the lock time is less than
. It consumes 5.3mA from a 3V power supply. The conversion gain and OIP3 of the IF mixer block are 3.6dB and -11.3dBm. It consumes 5.3mA. The 3dB frequencies of the VGA are greater than 250MHz for all gain settings. The designed VGA consumes 10mA. The designed RF block exhibits a gain of 14.93dB and an OIP3 of 6.97dBm. The image and carrier suppressions are 35dBc and 31dBc, respectively. It consumes 63.4mA. The designed circuits are under fabrication using a
CMOS process. The designed entire chip consumes 84mA from a 3V supply, and its area is
Design of Digital Calibration Circuit of Silicon Pressure Sensors
Kim, Kyu-Chull ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 245~252
We designed a silicon pressure sensor interface circuit with digital calibration capability. The interface circuit is composed of an analog section and a digital section. The analog section amplifies the weak signal from the sensor and the digital section handles the calibration function and communication function between the chip and outside microcontroller that controls the calibration. The digital section is composed of I2C serial interface, memory, trimming register and controller. The I2C serial interface is optimized to suit the need of on-chip silicon microsensor in terms of number of IO pins and silicon area. The major part of the design is to build a controller circuit that implements the optimized I2C protocol. The designed chip was fabricated through IDEC's MPW. We also made a test board and the test result showed that the chip performs the digital calibration function very well as expected.
Study on the Selection Criteria of 3D Collision Detection Model
Kang, Yun-Mi ; Park, Young-B. ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 253~259
In a good 3D engine, objects interactions are similar to those of real-world. Collision is one of the interactions. It includes whether collision took place or not, where collision took placed, and reaction after collision took place. More precise collision detection needs more time. If there exist required precision, detection time can be controlled by choosing appropriate detection model. Therefore, we need a selection mechanism for the collision detection with respect to required precision and detection time. In this paper, a collision detection model with seven different precision levels is examined. And relationship between detection time and precision is analyzed. Consequently, we propose a selection mechanism for collision detection model.
The Effect of NIC Buffer Size of Web Server on the Performance of LAN
Kim, Jin-Hee ; Sin, Bum-Suk ; Kwon, Kyung-Hee ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 260~264
Among many factors to affect the network performance, this paper analyses how the buffer size of NIC(Network Interface Card) can affect web server and LAN(Local Area Network). We use the ns-2 which is defacto network simulation tool to observe the changes in drop rate, throughput, RTT(Round Trip Time), effective throughput depending on varying buffer sizes. And we analyse the effect of NIC buffer size on the web traffic in Ethernet.
Improving the Performance of Web Server in Ethernet by Controlling the RTO
Kim, Jin-Hee ; Kwon, Kyung-Hee ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 265~270
We divide networks of an organization into internal network and external network to distribute the load of web server, and allocate separate web server for each network. The performance of web server for internal networks can be affected seriously by RTO(Retransmission Timeout). The value of RTO set by default in the OS of an web server is so large that it degrades the performance of web server. Therefore, this paper suggests not useing but applying conventional algorithm to calculate RTO, but to apply newly controlled value of RTO, and it showed improvement of the performance of web server.
An Adaptive Pseudomedian Filter for the Ultrasound Medical Image Processing
Eo, Jin-Woo ; Hur, Eun-Seok ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 271~280
This paper presents an effective method to segment objects from the ultrasound medical image which is inherently corrupted by speckle noise. In order to reduce the speckle noise morphological opening was used as preprocessing. For the preprocessed image, sample variance of neighborhood pixels is to be computed to classify where the pixel is located on the edge region or homogeneous region. Then pseudomedian filtering with different window size is taken according to the region classified, named adaptive pseudomedian filter. Various experimental results were presented to prove superiority of the proposed filter.
A study on Radiowave Interference Analysis Algorithms for Enhancement of Radio-Frequency Management System
Kim, Yu-Mi ; Rhee, Ill-Keun ; Bae, Suk-Hee ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 281~287
This paper proposed an improvement scheme for effective usage of radio-frequency management system(RFMS), which has been operated to facilitate national spectrum management and monitoring in Korea. Based on the wave propagation models, interference analysis algorithms, and sharing criteria recommended by ITU-R, we derived criteria for the automated selection of the channel interference analysis algorithms and sharing conditions adequate to the environment to be analysed. Then using the obtained criteria, computer and program has been made and shown to select the most appropriate propagation models, interference analysis algorithms, and sharing criteria from the ones provided in RFMS, with the illustrative example.
Endowment of Duplicated Serial Number for Window-controlled Selective-repeat ARQ
Park, Jin-Kyung ; Shin, Woo-Cheol ; Ha, Jun ; Choi, Cheon-Won ;
Journal of IKEEE, volume 7, issue 2, 2003, Pages 288~298
We consider a window-controlled selective-repeat ARQ scheme for error control between two adjacent nodes lying on a communication path. In this scheme, each packet to be transmitted is endowed with a serial number in a cyclic and sequential fashion. In turn, the transmitting node is not allowed to transmit a packet belonging to a window before every packet in the previous window is positively acknowledged. Such postponement of packet transmission incurs a degradation in throughput and delay performance. In this paper, aiming at improving packet delay performance, we employs a supplement scheme in which a serial number is duplicated within a frame. Classifying duplication rules into fixed, random and adaptive categories, we present candidate rules in each category and evaluate the packet delay performance induced by each duplication rule. From numerical examples, we observe that duplicating serial numbers, especially ADR-T2 effectively reduces mean packet delay for the forward channel characterized by a low packet error rate. We also reveal that such delay enhancement is achieved by a high probability of hitting local optimal window size.