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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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Journal of IKEEE
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Journal DOI :
Institude of Korean Electrical and Electronics Engineers
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Volume & Issues
Volume 8, Issue 2 - Dec 2004
Volume 8, Issue 1 - Jul 2004
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Design of Finite Field Multiplier based on KOA
Byun, Gi-Young ; Na, Gi-Soo ; Kim, Heung-Soo ;
Journal of IKEEE, volume 8, issue 1, 2004, Pages 1~11
This paper proposes new multiplicative techniques over finite field, by using KOA. At first, we regenerate the given polynomial into a binomial or a trinomial to apply our polynomial multiplicative techniques. After this, the product polynomial is archived by defined auxiliary polynomials. To perform multiplication over
by product polynomial, a new mod
method is induced. Using the proposed operation techniques, multiplicative circuits over
are constructed. We compare our circuit with the previous one as proposed by Parr. Since Parr's work is premised on
, it will not apply to general cases. On the other hand, the our work more expanded adaptive field in case m=3n.
Design of a Timing Error Detector Using Built-In current Sensor
Kang, Jang-Hee ; Jeong, Han-Chul ; Kwak, Chol-Ho ; Kim, Jeong-Beom ;
Journal of IKEEE, volume 8, issue 1, 2004, Pages 12~21
Error control is one of major concerns in many electronic systems. Experience shows that most malfunctions during system operation are caused by transient faults, which often mean abnormal signal delays that may result in violations of circuit element timing constraints. This paper presents a novel CMOS-based concurrent timing error detector that makes a flip-flop to sense and then signal whether its data has been potentially corrupted or not by a setup or hold timing violation. Designed circuit performs a quiescent supply current evaluation to determine timing violation from the input changes in relation to a clock edge. If the input is too close to the clock time, the resulting switching transient current in the detection circuit exceeds a reference threshold at the instant of the clock transition and an error is flagged. The circuit is designed with a
standard CMOS technology at a 2.5 V supply voltage. The validity and effectiveness are verified through the HSPICE simulation. The simulation results in this paper shows that designed circuit can be used to detect setup and hold time violations effectively in clocked circuit element.
A Study on the Constructions MOVAGs based on Operation Algorithm for Multiple Valued Logic Function and Circuits Design using T-gate
Yoon, Byoung-Hee ; Park, Soo-Jin ; Kim, Heung-Soo ;
Journal of IKEEE, volume 8, issue 1, 2004, Pages 22~32
In this paper, we proposed MOVAG(Multi Output Value Array Graphs) based on OVAG by Honghai Jiang to construct multiple valued logic function The MDD(Muliple-valued Decision Diagra) needs many processing time and efforts in circuit design for given multi-variable function by D.M.Miller, and we designed a MOVAG which has reduce the data processing time and low complexity. We propose the construction algorithm and input matrix selection algorithm and we designed the multiple-valued logic circuit using T-gate and verified by simulation results.
Design of Quaternary Logic gate Using Double Pass-transistor Logic with neuron MOS Threshold gate
Park, Soo-Jin ; Yoon, Byoung-Hee ; Kim, Heung-Soo ;
Journal of IKEEE, volume 8, issue 1, 2004, Pages 33~38
A multi-valued logic(MVL) pass gate is an important element to configure multi-valued logic. In this paper, we designed the Quaternary MIN(QMIN)/negated MIN(QNMIN) gate, the Quaternary MAX(QMAX)/negated MAX(QNMAX) gate using double pass-transistor logic(DPL) with neuron
threshold gate. DPL is improved the gate speed without increasing the input capacitance. It has a symmetrical arrangement and double-transmission characteristics. The threshold gates composed by
down literal circuit(DLC). The proposed gates get the valued to realize various multi threshold voltages. In this paper, these circuits are used 3V power supply voltage and parameter of 0.35um N-Well 2-poly 4-metal CMOS technology, and also represented HSPICE simulation results.
Realization of Multi-purpose Coherent Monopulse Radar Simulator with Expandable Feature
Kim, Jae-Jun ; Lee, Jong-Pil ; Rhee, Ill-Keun ;
Journal of IKEEE, volume 8, issue 1, 2004, Pages 39~46
This paper presents the realization schemes for a multipurpose coherent mono-pulse radar Simulator with extendable features. We developed and installed the TSG(Timing Signal Generator) board which can simulate a mechanically rotate signal of antenna, an operation timing signal of pulse radar and target signal, to operate the simulator without real target in the indoor environment. Also, with the insertion of the radar signal processor, it came to be easy to achieve the addition of radar function algorithms, to rebuild or extend the multi-DSP Architecture into the simulator. Throughout the simulation results, we verified that the designed coherent mono-pulse radar simulator can exactly display a moving target on the realistic monitor(RD 9800).
A Design of a Ternary Storage Elements Using CMOS Ternary Logic Gates
Yoon, Byoung-Hee ; Byun, Gi-Young ; Kim, Heung-Soo ;
Journal of IKEEE, volume 8, issue 1, 2004, Pages 47~53
We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are composed with ternary voltage mode NMAX, NMIN, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.35um CMOS technology and 3.3Volts supply voltage. The architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.
Current-mode CMOS Multiplier
Na, Gi-Soo ; Byun, Gi-Young ; Kim, Heung-Soo ;
Journal of IKEEE, volume 8, issue 1, 2004, Pages 54~62
In this paper, we discuss on the design of a current mode CMOS multiplier circuit over
. Using the standard basis, we show the variation of vector representation of multiplicand by multiplying primitive element α, which completes the multiplicative process. For the
multiplicative circuit design, we design GF(3) adder and multiplier circuit using current mode CMOS technology and get the simulation results. Using the basic gates - GF(3) adder and multiplier, we build the
multiplier circuit and show the examples for the case m=3. We also propose the assembly of the operation blocks for a complete
multiplier. Therefore, the proposed circuit is easily extensible to other p and m values over
and has advantages for VLSI implementation. We verify the validity of the proposed circuit by functional simulations and the results are provided.
Prediction of Dynamic Power Consumption and IR Drop Analysis by efficient current modeling
Han, Sang-Yeol ; Park, Sang-Jo ; Lee, Yun-Sik ;
Journal of IKEEE, volume 8, issue 1, 2004, Pages 63~72
The supply voltage has been drop rapidly and the total length of the wire increased exponentially in the nanometer SoC design environment. The ideal supply voltage was dropped sharply by the resistance and parasitic devices which stayed on the kilometers-long wire length. Even worse, it could severely affect the functional behavior of the block of the design. To analyze the effects of the long wire of the SoC while maintaining the accuracy, the modeling of the current and the RC conversion of the parasitic techniques are researched and applied. By these modeling and conversion, the multi-million gates HDTV Chipset can be analyzed within a day. The benchmark analysis of the HDTV SoC showed the superiority to the conventional methods in performance and accuracy.
Design of 5.8 GHz Wireless LAN Sub Harmonic Pumped Resistive Mixer
Yoo, Hong-Gil ; Kim, Wan-Sik ; Kang, Jeong-Jin ; Lee, Jong-Arc ;
Journal of IKEEE, volume 8, issue 1, 2004, Pages 73~78
In this paper, it is designed for 5.8GHz Wireless LAN sub harmonic resistive mixer. Sub harmonic resistive mixer is constituted by advantage of sub harmonic mixer and resistive mixer. Sub harmonic resistive mixers mix harmonics of LO with RF and obtain IF frequency. Therefore, it was possible to use decreasing LO frequency than conventional mixers. And, Sub harmonic resistive mixer has low IMD because of using unbiased channel resistance of GaAs FET. When LO power is 13dBm, the conversion loss of manufactured sub harmonic resistive mixer is 10.67 dB. And IIP3 of mixer is 21.5dBm.
Design of 5.8 GHz Wireless LAN Sub Harmonics Pumped Mixer Using Anti Parallel Diode Pair
Yoo, Hong-Gil ; Jang, Seok-Hwan ; Kang, Jeong-Jin ; Lee, Jong-Arc ;
Journal of IKEEE, volume 8, issue 1, 2004, Pages 79~85
In this paper, Sub harmonic mixer using anti-parallel diode pair is designed for 5.8 GHz Wireless LAN. Conventional mixers mix LO with RF and obtain IF signal from the difference between LO and RF. As frequency increase, LO signal is required increasing LO power, better phase noise, stable LO. But, using APDP, the SHP mixer mix the harmonics of LO signal. Therefore, Sub harmonic mixer is advantage that necessary LO signal frequency was used to operate the 1/2. When LO power is 3 dBm, the conversion loss of manufactured SHP mixer is 12.83 dB. The isolation of LO/IF, 2LO/IF, RF/IF and LO/RF is 39.17 dB, 58 dB, 34 dB, 67.9 dB. And IIP3 is 8 dBm.
Fabrication and Measurement of Triple U-shaped slot Microstrip Antenna in 5GHz band
Kang, Moon-Kyou ; Jung, Yoo-Keun ; Ju, Jeong-Min ; Jeong, Gyey-Teak ; Yoon, Joong-Han ; Kwak, Kyung-Sup ;
Journal of IKEEE, volume 8, issue 1, 2004, Pages 86~95
In this paper, we designed, fabricated, and measured antenna results consisting of previous research, that can handle from wireless using-LAN U-shaped slot antenna of HiperLAN bandwidth to ISM band of HiperLAN 1/2 & 5 GHz bandwidth. We presented a new model that structuresof basic U-shaped slot added the same thing twice.After the foam layer is inserted between ground plane and substrate, we got enough bandwidth for VSWR<1.5. The antenna gain was
. The radiation pattern got a stable pattern in frequency bandwidth.
A New Integral Variable Structure Regulation Controller for Robot Manipulators with Accurately Predetermined Output Performance
Lee, Jung-Hoon ;
Journal of IKEEE, volume 8, issue 1, 2004, Pages 96~107
In this paper, a new integral variable structure regulation controller(IVSRC) is designed by using a special integral sliding surface and a disturbance observer for the improved regulation control of highly nonlinear robot manipulators with prescribed output performance. The sliding surface having the integral state with a special initial condition is employed in this paper to exactly predetermine the ideal sliding trajectory from a given initial condition to origin without any reaching phase. And a continuous sliding mode input using the disturbance observer is also introduced in oder to effectively follow the predetermined sliding trajectory within the prescribed accuracy without large computation burden. The performance of the prescribed tracking accuracy to the predetermined sliding trajectory is clearly investigated in detail through the two theorems together with the closed loop stability. The design of the proposed IVSRC is separated into the performance design and robustness design in each independent link. The usefulness of the algorithm has been demonstrated through simulation studies on the regulation control of a two link manipulator under parameter uncertainties and payload variations, in view of no reaching phase, no overshoot, predetermined response with prescribed accuracy, easy change of output performance, separation of design phase, and so on.
Implementation of the Embedded System using the Laser for Measurement of Vehicle Speed and Distance
Kim, Yong-Kwon ; Choe, Jin-Kyu ; Ki, Jang-Geun ;
Journal of IKEEE, volume 8, issue 1, 2004, Pages 108~116
In this paper, the measurement system of speed and distance of vehicles using laser is implemented and verified through the outdoor test. The implemented system consists of a laser module and a control/speed-computation module. The Former is composed of a optics part, a transmit/receive part, and a LDC(Laser Detection and Counter), and the latter is a control part that controls the laser module and a speed computation part that calculates velocity of vehicles using a microcontroller. The algorithm to compute speed has been developed to consider characteristics of laser and surrounding conditions. The implemented system has been tested and verified on the high way, and the result shows stability of the system and accuracy of the algorithm.
Simultaneous Measurement of Strain and Temperature by use of Fiber Bragg Grating Written in an Erbium: Ytterbium-Doped Fiber
Jung, Jae-Hoon ;
Journal of IKEEE, volume 8, issue 1, 2004, Pages 117~120
We demonstrate a fiber-optic sensor scheme, capable of the simultaneous measurement of strain and temperature using a single fiber Bragg grating written in an erbium: ytterbium-doped fiber. This novel and compact fiber grating based sensor scheme can be used for synchronous measurement of strain and temperature over ranges of
with rms errors of
, respectively. The simple and low-cost sensor approach has a considerable potential, particularly for wide-range strain sensing applications in which high resolution is not required.
Spectral Analysis of Arrayed Waveguide Grating
Jung, Jae-Hoon ;
Journal of IKEEE, volume 8, issue 1, 2004, Pages 121~127
We performed the spectrum analysis of arrayed waveguide grating using Fresnel Kirchhoff diffraction formula and its approximated Fraunhofer diffraction equation and applied both methods to 16 channel and 40 channel models. We presented the spectra and found out the limitations of Fraunhofer diffraction in analysis of arrayed waveguide grating and compared the errors coming from Fraunhofer diffraction approximation and due to imperfection during the fabrication process.
Sliding-DFT based multi-channel phase measurement FPGA system
Eo, Jin-Woo ; Chang, Tae-Gyu ;
Journal of IKEEE, volume 8, issue 1, 2004, Pages 128~135
This paper proposes a phase measurement algorithm which is based on the recursive implementation of sliding-DFT. The algorithm is designed to have a robust behavior against the erroneous factors of frequency drift, additive noise, and twiddle factor approximation. The size of phase error caused by the finite wordlength implementation of DFT twiddle factors is shown significantly lower than that of magnitude error. The drastic reduction of the phase error is achieved by the exploitation of the quadruplet symmetry characteristics of the approximated twiddle factors in the complex plane. Four channel power-line phase measurement system is also designed and implemented based on the time-multiplexed sharing architecture of the proposed algorithm. The operation of the developed system is also verified by the experiment performed under the test environment implemented with the multi-channel function generator and the on-line interfaced host processor system. The proposed algorithm's features of phase measurement accuracy and its robustness against the finite wordlength effects can provide a significant impact especially for the ASIC or microprocessor based embedded system applications where the enhanced processing speed and implementation simplicity are crucial design considerations.
A Study on AC Modeling of the ESD Protection Devices
Choi, Jin-Young ;
Journal of IKEEE, volume 8, issue 1, 2004, Pages 136~144
From the AC analysis results utilizing a two dimensional device simulator, the ac equivalent-circuit modeling of the ESD protection devices is executed. It is explained that the ac equivalent circuit of the NMOS protection transistor is modeled by a rather complicated form and that, depending on the frequency range, the error can be large if it is modeled by a simple RC serial circuit. It is also shown that the ac equivalent circuit of the thyristor-type pnpn protection device can be modeled by a simple RC serial circuit. Based on the circuit simulations utilizing the extracted equivalent circuits, the effects of the parasitics in the protection device on the characteristics of LNA are examined when the LNA, which is one of the important RF circuits, is equipped with the protection device. It is explained that a large error can result in estimating the circuit characteristics if the NMOS protection transistor is modeled by a simple capacitor. It is also confirmed that the degradation of the LNA characteristics by incorporating the ESD protection device can be reduced a lot by adopting the suggested pnpn device.
A Design of Low Power Digital Matched Filter using Rounding for IMT-2000 Communication Systems
Park, Ki-Hyun ; Ha, Jin-Suk ; Nam, Ki-Hun ; Cha, Jae-Sang ; Lee, Kwang-Youb ;
Journal of IKEEE, volume 8, issue 1, 2004, Pages 145~151
For wide-band spread spectrum communication systems such as IMT-2000, a digital matched filter is a key device for rapid spreading code synchronization. Although a digital matched filter can be implemented easily, large power consumption at the higher chip rate and large summation delay of longer chip length are the bottleneck of practical use. In this paper, we propose a optimized partial correlation digital matched filter structure which can be constructed of the so-called generalized hierarchical Golay sequence. a partial correlation structure can reduce the number of correlators, but enlarge the size of flip-flops. In this paper, The proposed approach focuses on efficient circuit size, power dissipation, maintaining the operating throughput. A proposed digital matched filter reduce the size of flip-flops by rounding method. and it reduces about 45 percentages of power dissipation and chip area as compared with digital matched filter which is not rounded. rounding. The proposed architecture was verified by using Xilinx FPGA.
The Study on the design of PWM IC with Power Device for SMPS application
Lim, Dong-Ju ; Koo, Yong-Seo ;
Journal of IKEEE, volume 8, issue 1, 2004, Pages 152~159
In this study, we design the one-chip PWM IC with high voltage power switch (300V class LDMOSFET) for SMPS (Switching Mode Power Supply) application. Reference circuits generate constant voltage(5V) in the various of power supply and temperature condition. Error amp. is designed with large DC gain
, unity frequency
. comparator is designed with 2 stage. Saw tooth generators operate with 20kHz oscillation frequency. Also, we optimize drift concentration & drift length of n-LDMOSFET for design of high voltage switching device. It is shown that simulation results have the breakdown voltage of 350V. (using ISE-TCAD Simulation tool). PWM IC with power switching device is designed with 2um design rule and Bi-DMOS technology.