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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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Journal of IKEEE
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Institude of Korean Electrical and Electronics Engineers
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Volume & Issues
Volume 8, Issue 2 - Dec 2004
Volume 8, Issue 1 - Jul 2004
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CMOS Clockless Wave Pipelined Adder Using Edge-Sensing Completion Detection
Ahn, Yong-Sung ; Kang, Jin-Ku ;
Journal of IKEEE, volume 8, issue 2, 2004, Pages 161~165
In this paper, an 8bit wave pipelined adder using the static CMOS plus Edge-Sensing Completion Detection Logic is presented. The clockless wave-pipelining algorithm was implemented in the circuit design. The Edge-Sensing Completion Detection (ESCD) in the algorithm is consisted of edge-sensing circuits and latches. Using the algorithm, skewed data at the output of 8bit adder could be aligned. Simulation results show that the adder operates at 1GHz in
CMOS technology with 3.3V supply voltage.
Design of a CMOS Time to Digital Converter with 25ps Resolution
Choi, Jin-Ho ; Kang, Jin-Ku ;
Journal of IKEEE, volume 8, issue 2, 2004, Pages 166~171
This paper describes a CMOS time to digital converter (TDC) that measures the interval between two signals and converts to a digital signal. There are various methods to measure the time interval. But several architectures have a limitation in resolution and in conversion time. Moreover, they have complex algorithms. But the proposed TDC circuit has achieved a high resolution (25ps) by using a high-speed digital sampler and simple algorithm. The sampler detects when input signals comes into the TDC and output is coded. The proposed multiphase clock generator was also implemented to achieve 25p resolution.
A Study on the Parallel Multiplier over
Han, Sung-Il ; Hwang, Jong-Hak ;
Journal of IKEEE, volume 8, issue 2, 2004, Pages 172~180
In this paper, a parallel Input/Output modulo multiplier, which is applied to AOTP(All One or Two Polynomials) multiplicative algorithm over
, has been proposed using neuron-MOS Down-literal circuit on voltage mode. The three-valued input of the proposed multiplier is modulated by using neuron-MOS Down-literal circuit and the multiplication and Addition gates are implemented by the selecting of the three-valued input signals transformed by the module. The proposed circuits are simulated with the electrical parameter of a standard
CMOS N-well doubly-poly four-metal technology and a single +3V supply voltage. In the simulation result, the multiplier shows 4 uW power consumption and 3 MHzsampling rate and maintains output voltage level in
A New Resource Allocation Algorithm of Functional Units to Minimize Power Dissipation
Lin, Chi-Ho ;
Journal of IKEEE, volume 8, issue 2, 2004, Pages 181~185
This paper reduces power dissipation with the minimum switching activity of functional units that have many operators. Therefore, it has more effects of power dissipation that operator dissipation to reduce power dissipation of whole circuit preferentially. This paper proposes an algorithm that minimize power dissipation in functional units operations that affect much as power dissipation in VLSI circuit. The algorithm has scheduled operands using power library that has information of all operands. The power library upgrades information of input data in each control step about all inputs of functional units and the information is used at scheduling process. Therefore, the power dissipation is minimized by functional units inputs in optimized data. This paper has applied algorithm that proposed for minimizing power dissipation to functional unit in high level synthesis. The result of experiment has effect of maximum 9.4 % for minimizing power dissipation.
Design of Automatic Document Classifier for IT documents based on SVM
Kang, Yun-Hee ; Park, Young-B. ;
Journal of IKEEE, volume 8, issue 2, 2004, Pages 186~194
Due to the exponential growth of information on the internet, it is getting difficult to find and organize relevant informations. To reduce heavy overload of accesses to information, automatic text classification for handling enormous documents is necessary. In this paper, we describe structure and implementation of a document classification system for web documents. We utilize SVM for documentation classification model that is constructed based on training set and its representative terms in a directory. In our system, SVM is trained and is used for document classification by using word set that is extracted from information and communication related web documents. In addition, we use vector-space model in order to represent characteristics based on TFiDF and training data consists of positive and negative classes that are represented by using characteristic set with weight. Experiments show the results of categorization and the correlation of vector length.
Analysis of the Phenomena Due to Resonant Frequency Mismatch in RFID Systems
Kwon, Duck-Ki ; Park, Jong-Tae ; Yu, Chong-Gun ;
Journal of IKEEE, volume 8, issue 2, 2004, Pages 195~206
In an RFID system, it is desirable to have both the reader and the transponder tuned to the same resonant frequency for efficient data transmission between them. Any difference in frequency will decrease the transponder coil voltage or the internal power supply voltage and will increase the possibility of zero modulation in the reader coil, which results in the reduction of the reading distance. In this paper, the phenomena caused by the frequency mismatch are theoretically analyzed and mathematically modelled. Several schemes to compensate for the frequency mismatch are also mentioned. The derived equations and analyzed theory on the data transmission between the reader and the transponder will be helpful to the development of RFID systems for many applications.
Sensitivity Analysis of Cache Coherence Protocol for Hierarchical-Bus Multiprocessor
Lee, Heung-Jae ; Choe, Jin-Kyu ; Ki, Jang-Geun ; Lee, Kyou-Ho ;
Journal of IKEEE, volume 8, issue 2, 2004, Pages 207~215
In a hierarchical-bus multiprocessor system, cache coherence protocol has effect on system performance. Under a particular cache coherence protocol, system performance can be affected by bus bandwidth, memory size, and memory block size. Therefore sensitivity analysis is necessary for the part of multiprocessor system. In this paper, we set up cache coherence protocol for hierarchical-bus multiprocessor system, and compute probability of state of protocol, and analyze sensitivity for part of system by simulation.
eCRM Agent System for Articles Automatic Classification System based on Naive Bayesian Classifier
Choi, Jung-Min ; Lee, Byoung-Soo ;
Journal of IKEEE, volume 8, issue 2, 2004, Pages 216~223
The customer's bulletin board is the important channel to get opinions from customers directly. The effective management of the bulletin board for the customer improves the reliance by providing the best replies and by accepting opinions of the customer and furthermore, that can raise the customer's reliance of the whole shopping mall is the important eCRM method. But, the present mostly customer's bulletin board is been replied without any classifying about many kinds of question. Consequently, The shopping mall should do systematic management of the best professional reply about many kinds of question. In order to resolve this problem, we implement a classifier called Naive Bayesian classifier is classified automatically bulletin board for eCRM of shopping mall.
Design and Implementation of Wire and Wireless Integrated System for Residential Parking Permit Program
Lee, Sang-Soon ; Lee, Byoung-Soo ;
Journal of IKEEE, volume 8, issue 2, 2004, Pages 224~232
Because vehicles increases very rapidly by elevation of people living standard since 1995 years, become parking space of residential street poorly and most vehicles is doing unlawfulness parking to two faces road. So, was placed popular enmity and administration's difficulty by operation of system that have been enforcing Resident Priority Parking System in each ward office since 1996 years, but is not computerized. In this paper examines about GIS technology, wire and wireless communication technology, character recognition technology etc. that is base technology necessary to Design and Implementation Wire and Wireless Integrated System for Resident Priority Parking System. Explain main process, That is registration, assignment, control, traction process. And see execution appearance of implementation system. Operation of integrated system is considered very rapidly regulation illegal parking and Illegal parking expect on the decrease.