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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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Journal of the Korean Institute of Electrical and Electronic Material Engineers
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Journal DOI :
The Korean Institute of Electrical and Electronic Material Engineers
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Volume & Issues
Volume 13, Issue 12 - Nov 2000
Volume 13, Issue 11 - Nov 2000
Volume 13, Issue 9 - Sep 2000
Volume 13, Issue 10 - Sep 2000
Volume 13, Issue 8 - Aug 2000
Volume 13, Issue 7 - Jul 2000
Volume 13, Issue 6 - Jun 2000
Volume 13, Issue 5 - Apr 2000
Volume 13, Issue 4 - Apr 2000
Volume 13, Issue 3 - Mar 2000
Volume 13, Issue 2 - Feb 2000
Volume 13, Issue 1 - Jan 2000
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Manipulation of Microstructures of in-situ Phosphorus-Doped Poly Silicon Films deposited on Silicon Substrate Using Two Step Growth of Reduced Pressure Chemical Vapor Deposition
Journal of the Korean Institute of Electrical and Electronic Material Engineers, volume 13, issue 2, 2000, Pages 95~100
For the well-controlled growing in-situ heavily phosphorus doped polycrystalline Si films directly on Si wafer by reduced pressure chemical vapor deposition, a study is made of the two step growth. When in-situ heavily phosphorus doped Si films were deposited directly on Si (100) wafer, crystal structure in the film is not unique, that is, the single crystal to polycrystalline phase transition occurs at a certain thickness. However, the well-controlled polycrtstalline Si films deposited by two step growth grew directly on Si wafers. Moreover, the two step growth, which employs crystallization of grew directly on Si wafers. Moreover, the two step growth which employs crystallization of amorphous silicon layer grown at low temperature, reveals crucial advantages in manipulating polycrystal structures of in-situ phosphorous doped silicon.
The Analysis of Characteristics on n-channel Offset-gated poly-Si TFT's with Electical Stress
Journal of the Korean Institute of Electrical and Electronic Material Engineers, volume 13, issue 2, 2000, Pages 101~105
The effects of electrical on n-channel offset gated poly-Si TFT's have been investigated. It is observed that the electrical field near the drain region in offset devices is smaller than that of conventional device by simulation results. The variation rate of threshold voltage and subthreshold slope decrease with increasing the offset length because of lowering the electric field near the drain region. The offset gated poly-Si TFT's have been probed effective in reducing the degradation rate of device performance under electrical stressing.
A Study on the TCAD Simulation to Predict the Latchup Immunity of High Energy Ion Implanted CMOS Twin Well Structures
Journal of the Korean Institute of Electrical and Electronic Material Engineers, volume 13, issue 2, 2000, Pages 106~113
This study describes how a properly calibrated simulation method could be used to investigate the latchup immunity characteristics among the various high energy ion implanted CMOS twin well (retro-grade/BILLI/BL) structures. To obtain the accurate quantitative simulation analysis of retrograde well, a global tuning procedure and a set of grid specifications for simulation accuracy and computational efficiency are carried out. The latchup characteristics of BILLI and BL structures are well predicted by applying a calibrated simulation method for retrograde well. By exploring the potential contour, current flow lines, and electron/hole current densities at the holding condition, we have observed that the holding voltage of BL structure is more sensitive to the well design rule (p+to well edge space /n +to well edge space) than to the retrograde well itself.
A Study on the Silicon Etching Characteristics in ECR using
Journal of the Korean Institute of Electrical and Electronic Material Engineers, volume 13, issue 2, 2000, Pages 114~119
Etch characteristics of SF6/CI2 electron cyclotron resonance (ECR) plasmas have been investigated. Surface reaction of gas plasma with polysilicon was also analysed using X-ray photoelectron spectroscopy (XPS). At the same time, the relationship between surface reaction and the etched profile of polysilicon was examined using XPS. The etch rate of polysilicon and oxide increases with increasing flow rate of SF6 in the SF6/CI2 gas mixture, and tis selectivity also increase also increase. It was also found that as increasing flow rate of SF6 in the SF6/CI2 gas mixture, the atomic% of chlorine detected at surface region decrease, but F and S contents increase. At the same time, when the mixing ratio of SF6 gas increases, the anisotropy of etched polysilicon is sharply decreased in the 0%~10% range of the SF6 mixing ratio, but is rarely varied in the range over 10%, in spite of the large variations in flow rates. It can be explained that the bonding of S-Si due to SiSx(x
2) compound formed on the etched surface suppress the formation of Si-Cl and 'or Si-F bonding in the silicon etching.
Study on Improved Switching Characteristics of LIGBT by the Trap Injection
Journal of the Korean Institute of Electrical and Electronic Material Engineers, volume 13, issue 2, 2000, Pages 120~124
In this paper, the effects of trap distribution on switching characteristis of a lateral insulated gate bipolar transistor (LIGBT) are investigated. The simulations are performed in order to to analyze the effect of the positon, width and concentration of trap distribution model with a reduced minority carrier lifetime using 2D device simulator MEDICI. The turn off time for the proposed LIGBT model A with the trap injection is 0.8
. These results indicate the improvement of about 2 times compared with the conventional LIGBT. It is shown that the trap distribution model is very effective to reduce the turn-off time with a little increasing of on-state voltage drop.
High-Quality Epitaxial Low Temperature Growth of In Situ Phosphorus-Doped Si Films by Promotion Dispersion of Native Oxides
Journal of the Korean Institute of Electrical and Electronic Material Engineers, volume 13, issue 2, 2000, Pages 125~130
Two step growth of reduced pressure chemical vapor eposition has been successfully developed to achieve in-situ phosphorus-doped silicon epilayers, and the characteristic evolution on their microstructures has been investigated using scanning electron microscopy, transmission electron microscopy, and secondary ion mass spectroscopy. The two step growth, which employs heavily in-situ P doped silicon buffer layer grown at low temperature, proposes crucial advantages in manipulating crystal structures of in-situ phosphorus doped silicon. In particular, our experimental results showed that with annealing of the heavily P doped silicon buffer layers, high-quality epitaxial silicon layers grew on it. the heavily doped phosphorus in buffer layers introduces into native oxide and plays an important role in promoting the dispersion of native oxides. Furthermore, the phosphorus doping concentration remains uniform depth distribution in high quality single crystalline Si films obtained by the two step growth.
CMP Slurry Induction Properties of Silicate Oxides Deposited on Silicon Wafer
Journal of the Korean Institute of Electrical and Electronic Material Engineers, volume 13, issue 2, 2000, Pages 131~136
We have investigated the slurry induced metallic contaminations of undoped and doped silicate oxides surface on CMP cleaning process. The metallic contaminations by CMP slurry were evaluated in four different oxide films, such as plasma enhanced tetra-ethyl-orthyo-silicate glass(PE-TEOS), O3 boro-phos-pho-silicate glass(O3-BPSG), PE-BPSG, and phospho-silicate glass(PSG). All films were polished with KOH-based slurry prior to entering the post-CMP cleaner. The Total X-Ray fluorescence(TXRF) measurements showed that all oxide surfaces are heavily contaminated by potassium and calcium during polishing which is due to a CMP slurry. The polished O3-BPSG films presented higher potassium and calcium contaminations compared to PE-TEOS because of a mobile ions gettering ability of phosphorus. For PSG oxides, the slurry induced mobile ion contamination increased with an increase of phosphorus contents. In addition, the polishing removal rate of PSG oxides had a linear relationship as a function of phosphorus contents.
Sintering and Dielectric of
Ceramics with the Effect of Y/Mn Ratio
Journal of the Korean Institute of Electrical and Electronic Material Engineers, volume 13, issue 2, 2000, Pages 137~142
The sintering and electrical properties of YMnO3 bulk ceramics were investigated with Y/Mn ratios(Mn rich ;0.80/1.20, 0.90/1.10, 0.95/1.05, and Y rich ; 1.00/1.00, 1.05/0.95, 1.10/0.90). The crystal structure of samples showed a hexagonal structure, and the sample of Y/Mn = 0.95/1.05 indicated higher c-axis oriented peak than other samples. In the case of Mn rich samples, the grain sizes were about 7.8
and they showed 95% of theoretical density. Whereas, in the case of Y rich samples, the grain sizes were about 2.3
and they showed 86%. The dielectric constant and dissipation factor of the Mn rich samples were smaller than those of the Y rich samples. The samples of Y/Mn = 0.90/1.10 showed the lowest a dissipation factor, and their dielectric constant, dissipation factor and Curie temperature were 36, 0.0136 and 68
Capacitor characteristics of SBT Ferroelectric Thin Films depending on substrate conditions
Journal of the Korean Institute of Electrical and Electronic Material Engineers, volume 13, issue 2, 2000, Pages 143~150
thin films with various compositions(x=0.7, 0.8, 1, y=0.3, 0.4) were prepared by sol-gel method. The film with moled ratio of 0.8:2.3:2.0 in Sr/Bi/Ta, which was deposited on Pt/SiO2/Si (100), showed better ferroelectric properties than other films. To investigate substrate effects, the same compositions were spin coated on Pt/Ti/SiO2/Si (100) substrates. At an applied voltage of 5V, the dielectric constant(
r), remanent polarization (2Pr) and coercive field (Ec) of the Sr0.8Bi2.3Ta2O9+
thin film prepared on Pt/Ti/SiO2/Si (100) were about 296, 24
and Ec of 49kV/cm respectively. Both SBT films firred at 80
revealed no fatigue up to 1010 cycles. Retention characteristics of these capacitors showed no degradation up to 104 sec.
Effects of alignment layer on pretilt generation and electrical characteristics for nematic liquid crystal by using photo-alignment techniques
Journal of the Korean Institute of Electrical and Electronic Material Engineers, volume 13, issue 2, 2000, Pages 151~156
Effects of alignment layers on pretilt nagle generation and electrical characteristics in nematic liquid crystal(NLC) by using photo-alignment techniques on polyimide PI) surface with side chain were studied. The generated pretilt angle of the NLC on rubbed PI surface with 1-layer is almost the same as that with the 2-layers. However, the generated pretilt angle of the NLC on photo-induced PI surface with 2-layers is larger than that with the 1-layer. The different mechanism of pretilt generation in NLC was observed on the rubbing and photo-alignment method. Therefore, the pretilt angle of the NLC on photo-induced PI surface is attributed to surface roughness due to photo-dissociation on the polymer with UV light irradiation on PI surface. We observed the same characteristics of voltage-transmittance (V-T) and response time for 1- and 2-layers on PI surface. Consequently, we sugest that the VHR of photo-aligned TN-LCD is higher than that of the rubbing-aligned TN-LCD.
Electro-optical characteristics of photo-aligned TN-LCD using a new photo-dimerization method
Journal of the Korean Institute of Electrical and Electronic Material Engineers, volume 13, issue 2, 2000, Pages 157~162
The electro-optical characteristics of TN(twisted nematic)-LCD(liquid crystal display) with photo-dimerized on a PMCh(poly(4'methacryoyloxylchalcone)) surface using a new photo-dimerization method was studied. The excellent voltage-transmittance(V-T) curve of TN-LCD with photo-dimerized on a PNCh surface for 1 min. using a new photo-dimerization method was observed. Also, the voltage-hold-ing-ratio(VHR) of TN-LCD with photo-dimerized on a PMCh surface using a new photo-dimerization method is higher than that of conventional photo-dimerization method. Consequently, we suggest that the new photo-dimerization method. Consequently, we suggest that the new photo-dimerization method for LC aligning is the most promising rubbing-free techniques.
The characteristics of anti-erosion for MgO protecting layer in plasma display panel
Journal of the Korean Institute of Electrical and Electronic Material Engineers, volume 13, issue 2, 2000, Pages 163~169
In this paper, we showed the erosion characteristic of MgO protector layer releated to lifetime of plasma display panel(PDP). We observed MgO erosion characteristic as a functions of deposition conditions, pressure and distance between electrodes. In RIE condition of Xe gas, the lowest erosion rate appears in the conditions of no heating bias voltage -30V and pressure 5mtorr. In general, as deposition rate increases, erosion rate decreases. In real panel, when the gap distance between electrodes is narrow and the pressure is low, the heavy plasma damage appears. Also, the surfaces between electrodes and on the bus electrode are extremely damaged.
DC Performance of
Sn Cable Joints with multi-interfaces
Journal of the Korean Institute of Electrical and Electronic Material Engineers, volume 13, issue 2, 2000, Pages 170~176
The joints with multi-interfaces was expected to have low DC resistance compared with those with single interface. The small size joint specimens joined with Nb3Sn sub-cables were fabricated to investi-gate the DC performance in the range of 0 to 600A transport current without external magnetic field. The joints with multi-interfaces have a few n-Ohm resistance, which is much lower than that of single lap joint. Because the interfaces between sub-cables of multi-interfaced joint are more complicated than those of single-interfaced joint, the soldering condition between sub-cables is very effective on the joint DC resistance.
Characteristics of Surface Flashover on Partially Immersed of Spacer in Liquid Nitrogen
Journal of the Korean Institute of Electrical and Electronic Material Engineers, volume 13, issue 2, 2000, Pages 177~182
Composite insulation system of liquid nitrogen and solid spacer is widely applied in high temperature superconduction power machine. This study has three step procedure. As follow, first step is composition of parallel deposited electrode and vertically deposited electrode along the direction of immersion in liquid nitrogen(LN2). Second step is investigation into surface flashover voltage of solid spacer under partially immersed in LN2, and last step is comparison the result of this research with that of fully immersed in LN2 and at cryogenic temperature gaseous nitrogen(GN2). This result presented that surface flashover voltage along solid spacer half immersed in LN2 was almost the same as that of fully immersed spacer when the thickness of spacer(t) was t<10mm. In the case of t> 10mm, however, spacer flashover voltage was equal to that obtained in GN2 at cryogenic temperature. And the immersed direction functions as role of deciding the difference of surface flashover voltage.