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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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Journal of the Microelectronics and Packaging Society
Journal Basic Information
Journal DOI :
The Korean Microelectronics and Packaging Society
Editor in Chief :
Volume & Issues
Volume 10, Issue 4 - Dec 2003
Volume 10, Issue 3 - Sep 2003
Volume 10, Issue 2 - Jun 2003
Volume 10, Issue 1 - Mar 2003
Selecting the target year
Preparation and Characterization of Heating Element for Inkjet Printer
Journal of the Microelectronics and Packaging Society, volume 10, issue 3, 2003, Pages 1~7
The crystallized stable cobalt silicide
films were prepared on
substrates for the application of inkjet printing head as a heating element with omega shape. The structural images and temperature resistance coefficient were investigated. The value of temperature resistance coefficient of the heating element was found to be about
. The maximum power of the heating element was 2 W at the applied voltage of 2 V, 10 kHz in frequency and
in pulse width. From the investigation of fatigue property according to the repeated applied voltages, there was no drastic changes in the resistances of heating element under the condition of
pulsed cycles at below 15 V biased voltage. In contrast, the resistance of heating element was greatly increased at
pulsed cycles when the heating element was operated at 17 V.
Effects of Silica Filler and Diluent on Material Properties of Non-Conductive Pastes and Thermal Cycling Reliability of Flip Chip Assembly
Jang, Kyung-Woon ; Kwon, Woon-Seong ; Yim, Myung-Jin ; Paik, Kyung-Wook ;
Journal of the Microelectronics and Packaging Society, volume 10, issue 3, 2003, Pages 9~17
In this paper, thermo-mechanical and rheological properties of NCPs (Non-Conductive Pastes) depending on silica filler contents and diluent contents were investigated. And then, thermal cycling (T/C) reliability of flip chip assembly using selected NCPs was verified. As the silica filler content increased, thermo-mechanical properties of NCPs were changed. The higher the silica filler content was added, glass transition temperature (
) and storage modulus at room temperature became higher. While, coefficient of thermal expansion (CTE) decreased. On the other hand, rheological properties of NCPs were significantly affected by diluent content. As the diluent content increased, viscosity of NCP decreased and thixotropic index increased. However, the addition of diluent deteriorated thermo-mechanical properties such as modulus, CTE, and
. Based on these results, three candidates of NCPs with various silica filler and diluent contents were selected as adhesives for reliability test of flip chip assemblies. T/C reliability test was performed by measuring changes of NCP bump connection resistance. Results showed that flip chip assembly using NCP with lower CTE and higher modulus exhibited better T/C reliability behavior because of reduced shear strain in NCP adhesive layer.
Effects of Surface Finishes on the Low Cycle Fatigue Characteristics of Sn-based Pb-free Solder Joints
Journal of the Microelectronics and Packaging Society, volume 10, issue 3, 2003, Pages 19~27
finishes of PCB laminates are important in the solder joint reliability of flip chip package because the types and thicknesses of intermetallic compound(IMC), and compositions and hardness of solders are affected by them. In this study, effects of surface finishes of PCB on the low cycle fatigue resistance of Sn-based lead-free solders; Sn-3.5Ag, Sn-3.5Ag-XCu(X=0.75, 1.5), Sn-3.5Ag-XBi(X=2.5, 7.5) and Sn-0.7Cu were investigated for the Cu and Au/Ni surface finish treatments. Displacement controlled room temperature lap shear fatigue tests showed that fatigue resistance of Sn-3.5Ag-XCu(X=0.75, 1.5), Sn-3.5Ag and Sn-0.7Cu alloys were more or less the same each other but much better than that of Bi containing alloys regardless of the surface finish layer used. In general, solder joints on the Au/Ni finish showed better fatigue resistance than those on the Cu finish. Cross-sectional fractography revealed microcracks nucleation inside of the interfacial IMC near the solder mask edge, more frequently on the Cu than the Au/Ni surface finish. Macro cracks followed the solder/IMC interface in the Bi containing alloys, while they propagated in the solder matrix in other alloys. It was ascribed to the Bi segregation at the solder/IMC interface and the solid solution hardening effect of Bi in the
Effects of Microstructure on the Creep Properties of the Lead-free Sn-based Solders
Journal of the Microelectronics and Packaging Society, volume 10, issue 3, 2003, Pages 29~35
The Sn-based lead-free solders with varying microstructure were prepared by changing the cooling rate from the melt. Bulky as-cast SnAg, SnAgCu, and SnCu, alloys were cold rolled and thermally stabilized before the creep tests so that there would be very small amount of microstructural change during creep (TS), and thin specimens were water quenched from the melt (WQ) to simulate microstructures of the as-reflowed solders in flip chips. Cooling rates of the WQ specimens were 140∼150 K/sec, and the resultant
globule size was 5∼10 times smaller than that of the TS specimens. Subsequent creep tests showed that the minimum strain rate of TS specimens was about
times higher than that of the WQ specimens. Fractographic analyses showed that creep rupture of the TS-SnAgCu specimens occurred by the nucleation of voids on the
particles in the matrix, their subsequent growth by the power-law creep, and inter-linkage of microcracks to form macrocracks which led to the fast failure. On the other hand, no creep voids were found in the WQ specimens due to the mode III shear rupture coming from the thin specimens geometry.
Thermodynamic Issues of Lead-Free Soldering in Electronic Packaging
Journal of the Microelectronics and Packaging Society, volume 10, issue 3, 2003, Pages 37~42
In soldering of electronic packaging, the research on substituting lead-free solder materials for Pb-Sn alloys has become active due to environmental and health concerns over the use of lead. The reliability of the solder joint is very important in the development of solder materials and it is known that it is related to wettability of the solder over the substrate and microstructural evolution during soldering. It is also highly affected by type and extent of the interfacial reaction between solder and substrate and therefore, it is necessary to understand the interfacial reaction between solder and substrate completely. In order to predict the intermetallic compound (IMC) phase which forms first at the substrate/solder interface during the soldering process, a thermodynamic methodology has been suggested. The activation energy for the nucleation of each IMC phases is represented by a function of the interfacial energy and the driving force for phase formation. From this, it is predicted that the IMC phase with the smallest activation energy forms first. The grain morphology of the IMC at the solder joint is also explained by the calculations which use the energy. The Jackson parameter of the IMC grain with a rough surface is smaller than 2 but it is larger than 2 in the case of faceted grains.
Recent Technical Trend and Properties on Raw Materials of Substrates for Microelectronic Packages
Journal of the Microelectronics and Packaging Society, volume 10, issue 3, 2003, Pages 43~55
As the development of If industries and their electronic device manufacturing technology have been accelerated recently, the request for electronic devices with small size, light weight, and high performance has been inducing that electronic package and substrate (PCB) companies have to develop substrates with low cost, high dense I/O, excellent thermal properties and electrical properties. Therefore, world-wide chip makers have been setting their own severe reliability standards and requiring their suppliers to keep specification and to develop green, high frequency and high-performing substrates. Because properties of substrates are dependent mainly on their constituent materials, the application of them showing superior properties is expected to satisfy the customer's requirement. Therefore, substrate companies should ensure the superiority of materials and assure their competitive capability of substrates by analyzing the latest trends of technology and properties of the materials.
Study of Failure Mechanisms of Wafer Level Vacuum Packaging for MEMG Gyroscope Sensor
Journal of the Microelectronics and Packaging Society, volume 10, issue 3, 2003, Pages 57~65
In this study, we carry out reliability tests and investigate the failure mechanisms of the anodically bonded wafer level vacuum packaging (WLVP) MEMS gyroscope sensor. There are three failure mechanisms of WLVP: leakage, permeation and out-gassing. The leakage is caused by small dimension of the leak channel through the bonding interface and internal defects. The larger bonding width and the use of single crystalline silicon can reduce the leak rate. Silicon and glass wafer itself generates a large amount of outgassing including
, and organic gases. Epi-poly wafer generates 10 times larger amount of outgassing than SOI wafer. The sandblasting process in the glass increases outgassing substantially. Outgassing can be minimized by pre-baking of the wafer in the vacuum oven before bonding process. An optimum pre-baking temperature of the wafers would be between
SiC Synthesis by Using Sludged Si Power
Journal of the Microelectronics and Packaging Society, volume 10, issue 3, 2003, Pages 67~71
Sawing silicon ingot with abrasive slurry generates sludge that includes abrasive powders, cutting oil, and silicon powders. The abrasive powders and cutting oil are being separated and reused. Mixing the remained stodged silicon powders with carbon powders and subsequent heat-treatment are conducted to produce silicon carbide. The size of SiC whiskers and powders was smaller than the conventionally grown silicon carbide whiskers that were synthesized by adding micron-size metal impurities. Impurity related mechanism is attributed to the formation of the silicon carbide whiskers, as metal impurities are contained in the stodged silicon powders.
Thermophysical Properties of PWB for Microelectronic Packages with Solder Resist Coating Process
Journal of the Microelectronics and Packaging Society, volume 10, issue 3, 2003, Pages 73~82
Recently, PWB(Printed Wiring Board) has been recognized in the field of microelectronic package as core technology for designing or manufacturing. PWB is the structure stacked by several materials with different thermophysical properties, which shows the different CTEs(Coefficient or Thermal Expansions) during the fabrication process and causes a lot of defects such as warpage, shrinkage, dimension, etc. Thermal deformation of PWB is affected mainly by the volume change of solder-resist among fabrication parameters. Therefore, thermal deformation of PBGA and CSP consisting of 2 layers and 4 layers was studied with solder-resist process. When over 30% in volume fraction of solder-resist, thermal deformation of 2-layered PWB was min. 40% higher than that of 4-layered PWB because 4-layered PWB contained the layer with high toughness such as prepreg, which counterbalanced the thermal deformation of solder-resist. Otherwise, when below 30%, PWB showed similar thermal deformation without regard to layers and design.
Optoelectronic Properties of Semiconductor-Atomic Superlattice Diode for SOI Applications
Journal of the Microelectronics and Packaging Society, volume 10, issue 3, 2003, Pages 83~88
The optoelectronic characteristics of semiconducto-atomic superlattice as a function of deposition temperature and annealing conditions have been studied. The nanocrystalline silicon/adsorbed oxygen superlattice formed by molecular beam epitaxy(MBE) system. As an experimental result, the superlattice with multilayer Si-O structure showed a stable photoluminescence(PL) and good insulating behavior with high breakdown voltage. This is very useful promise for Si-based optoelectronics and quantum devices as well as for the replacement of silicon-on-insulator (SOI) in ultra-high speed and lower power CMOS devices in the future, and it can be directly integrated with silicon ULSI processing.
Electrical and Mechanical Properties of Cu(Mg) Film for ULSI Interconnect
Journal of the Microelectronics and Packaging Society, volume 10, issue 3, 2003, Pages 89~98
The electrical and mechanical properties of sputtered Cu(Mg) films are investigated for highly reliable interconnects. The roughness, adhesion, hardness and resistance to thermal stress of Cu(Mg) film annealed in vacuum at
for 30min were improved than those of pure Cu film. Moreover, the flat band voltage(V
) shift in the Capacitance-Voltage(C-V) curve upon bias temperature stressing(BTS) was not observed and leakage currents of Cu(Mg) into
were three times less than those of pure Cu. Because Mg was easy to react with oxide than Cu and Si after annealing, the Mg Oxide which formed at surface and interface served as a passivation layer as well.