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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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Journal of the Microelectronics and Packaging Society
Journal Basic Information
Journal DOI :
The Korean Microelectronics and Packaging Society
Editor in Chief :
Volume & Issues
Volume 15, Issue 4 - Dec 2008
Volume 15, Issue 3 - Sep 2008
Volume 15, Issue 2 - Jun 2008
Volume 15, Issue 1 - Mar 2008
Selecting the target year
Fabrication and Characterization of High Efficiency
Jang, Ji-Geun ; Shin, Sang-Baie ; Shin, Hyun-Kwan ; Ahn, Jong-Myoung ; Chang, Ho-Jung ; Ryu, Sang-Ouk ;
Journal of the Microelectronics and Packaging Society, volume 15, issue 2, 2008, Pages 1~6
New devices with the structure of ITO/2-TNATA/NPB/TCTA/CBP:
/BCP/SFC-137/LiF/Al were designed and fabricated to develop high efficiency green phosphorescent organic light emitting diodes and their electroluminescence properties were evaluated. Among the devices with different thicknesses of CBP in a range of
, the best luminance was obtained in the device with
-thick CBP host. Nearly saturated current efficiencies indicates that the maximum efficiency value can be obtained with CBP thicknesses of
. The current density, luminance, and current efficiency of the PhOLED(phosphorescent organic light emitting diode) with
layer at an applied voltage of 10V were
, and 25 cd/A, respectively. The maximum current efficiency was 40.5cd/A under the luminance of
. The peak wavelength and FWHM(full width at half maximum) in the electroluminescence spectral were 512nm and 60nm, respectively. The color coordinate was (0.28, 0.63) on the CIE (Commission Internationale de I'Eclairage) chart.
A Study on the Assembly Process and Reliability of COF (Chip-On-Flex) Using ACFs (Anisotropic Conductive Films) for CCM (Compact Camera Module)
Chung, Chang-Kyu ; Paik, Kyung-Wook ;
Journal of the Microelectronics and Packaging Society, volume 15, issue 2, 2008, Pages 7~15
In this paper, the Chip-On-Flex (COF) assembly process using anisotropic conductive films (ACFs) was investigated and the reliability of COF assemblies using ACFs was evaluated. Thermo-mechanical properties of ACFs such as coefficient of thermal expansion (CTE), storage modulus (E'), and glass transition temperature
were measured to investigate the effects of ACF material properties on the reliability of COF assemblies using ACFs. In addition, the bonding conditions for COF assemblies using ACFs such as time, temperature, and pressure were optimized. After the COF assemblies using ACFs were fabricated with optimized bonding conditions, reliability tests were then carried out. According to the reliability test results, COF assemblies using the ACF which had lower CTE and higher
showed better thermal cycling reliability. Consequently, thermo-mechanical properties of ACFs, especially
, should be improved for high thermal cycling reliability of COF assemblies using ACFs for compact camera module (CCM) applications.
Fabrication of Sn-Cu Bump using Electroless Plating Method
Moon, Yun-Sung ; Lee, Jae-Ho ;
Journal of the Microelectronics and Packaging Society, volume 15, issue 2, 2008, Pages 17~21
The electroless plating of copper and tin were investigated for the fabrication of Sn-Cu bump. Copper and tin were electroless plated in series on
diameter copper via to form approximately
height bump. In electroless copper plating, acid cleaning and stabilizer addition promoted the selectivity of bath on the copper via. In electroless tin plating, the coating thickness of tin was less uniform relative to that of electroless copper, however the size of Sn-Cu bump were uniform after reflow process.
Fabrication and Characterization of Polymer Light Emitting Diodes by Using PFO/PFO:MEH-PPV Double Emitting Layer
Chang, Young-Chul ; Shin, Sang-Baie ;
Journal of the Microelectronics and Packaging Society, volume 15, issue 2, 2008, Pages 23~28
To improve the external quantum efficiency by means of the optimization of the polymer light emitting diodes(PLEDs) structure, the PLED with ITO/PEDOT:PSS/(PFO)/PFO:MEH-PPV/LiF/Al structure were fabricated and investigated the electrical and optical properties for the prepared devices. ITO(indium tin oxide) and PEDOT:PSS [poly (3,4-ethylenedioxythiophene): poly(styrene sulfolnate)] were used as transparent anode film and hole transport materials, respectively. PFO[poly(9,9-dioctylfluorene)] and MEHPPV[poly(2-methoxy-5(2-ethylhe xoxy)-1,4-phenylenevinyle)] were used as the light emitting host and dopant materials. The doping concentration of MEH-PPV was 9wt% with thickness of about
. We investigated the dependence of the PFO thickness ranging from
on the electrical, optical properties of PLEDs. Among prepared PLED devices with different PFO thicknesses, the highest value of the luminance was obtained for the PLED device with
in thickness. As a result, the current density and luminance ware found to be about
at 13V, respectively. In addition, the luminance and current efficiency of PLED device with double emitting layer (PFO/PFO:MEH-PPV) were improved about 3 times compared with the one with single emitting layer (PFO:MEH-PPV).
Mechanical Reliability Issues of Copper Via Hole in MEMS Packaging
Choa, Sung-Hoon ;
Journal of the Microelectronics and Packaging Society, volume 15, issue 2, 2008, Pages 29~36
In this paper, mechanical reliability issues of copper through-wafer interconnections are investigated numerically and experimentally. A hermetic wafer level packaging for MEMS devices is developed. Au-Sn eutectic bonding technology is used to achieve hermetic sealing, and the vertical through-hole via filled with electroplated copper for the electrical connection is also used. The MEMS package has the size of
. The robustness of the package is confirmed by several reliability tests. Several factors which could induce via hole cracking failure are investigated such as thermal expansion mismatch, via etch profile, and copper diffusion phenomenon. Alternative electroplating process is suggested for preventing Cu diffusion and increasing the adhesion performance of the electroplating process. After implementing several improvements, reliability tests were performed, and via hole cracking as well as significant changes in the shear strength were not observed. Helium leak testing indicated that the leak rate of the package meets the requirements of MIL-STD-883F specification.
Reliability Studies on Cu/SnAg Double-Bump Flip Chip Assemblies for Fine Pitch Applications
Son, Ho-Young ; Kim, Il-Ho ; Lee, Soon-Bok ; Jung, Gi-Jo ; Park, Byung-Jin ; Paik, Kyung-Wook ;
Journal of the Microelectronics and Packaging Society, volume 15, issue 2, 2008, Pages 37~45
In this study, reliabilities of Cu (60 um)/SnAg (20 um) double-bump flip chip assemblies were investigated for the flip chip interconnections on organic substrates with 100 um pitch. After multiple reflows at
, bump contact resistances were almost same regardless of number of reflows and reflow temperature. In the high temperature storage test, there was no bump contact resistance change at
up to 2000 hours. However, bump contact resistances slightly increased at
due to Kirkendall voids formation. In the electromigration test, Cu/SnAg double-bump flip chip assemblies showed no electromigration until about 600 hours due to reduced local current density. Finally, in the thermal cycling test, thermal cycling failure mainly occurred at Si chip/Cu column interface which was found out the highest stress concentration site in the finite element analysis. As a result, Al pad was displaced out under thermal cycling. This failure mode was caused by normal compressive strain acting Cu column bumps along perpendicular direction of a Si chip.
The Effect of Abnormal Intermetallic Compounds Growth at Component on Board Level Mechanical Reliability
Choi, Jae-Hoon ; Ham, Hyon-Jeong ; Hwang, Jae-Seon ; Kim, Yong-Hyun ; Lee, Dong-Chun ; Moon, Jeom-Ju ;
Journal of the Microelectronics and Packaging Society, volume 15, issue 2, 2008, Pages 47~54
In this paper, we studied how and why did abnormal IMC growth at component affect on board level mechanical reliability. First, interfacial reactions between Sn2.5Ag0.5Cu solder and electrolytic Ni/Au UBM of component side were investigated with reflow times and thermal aging time. Also, to compare mechanical reliability of component level, shear energy was evaluated using the ball shear test conducted with variation of shear tip speed. Finally, to evaluate mechanical reliability of board level, we surface-mounted component fabricated with each condition on PCB side. After conducting of 3 point bending test and impact test, we confirmed solder joint crack mode using cross-sectioning and dye & pry penetration method.
Lifetime Estimation of a Bluetooth Module using Accelerated Life Testing
Son, Young-Kap ; Chang, Seog-Weon ; Kim, Jae-Jung ;
Journal of the Microelectronics and Packaging Society, volume 15, issue 2, 2008, Pages 55~61
This paper shows quantitative reliability evaluations of a Bluetooth module through extending previous qualitative methods limited to structure reliability tests and solder joint reliability tests for Bluetooth modules. Accelerated Life Testing (ALT) of the modules using temperature difference in temperature cycling as an accelerated stress was conducted for quantitative reliability evaluation under field environment conditions. Lifetime distribution parameters were estimated using the failure times obtained through the ALT, and then Coffin-Manson model was implemented. Results of the ALT showed that the failure mode of the modules was open and the failure mechanisms are both crack and delamination. The ALT reproduced the failure mode and mechanisms of failed Bluetooth modules collected from the field. Further, a quantitative reliability evaluation method with respect to various temperature differences in temperature cycling was proposed in this paper.
lifetime of the module for the temperature difference
using the proposed method would be estimated as about 4 years.
Effect of Si Wafer Ultra-thinning on the Silicon Surface for 3D Integration
Choi, Mi-Kyeung ; Kim, Eun-Kyung ;
Journal of the Microelectronics and Packaging Society, volume 15, issue 2, 2008, Pages 63~67
3D integration technology has been a major focus of the next generation of IC industries. In this study Si wafer ultra-thinning has been investigated especially for the effect of ultra-thinning on the silicon surface. Wafers were grinded down to
thickness and then grinded only samples were compared with surface treated samples in terms of surface roughness, surface damages, and hardness. Dry polishing or wet etching treatment has been applied as a surface treatment. Surface treated samples definitely showed much less surface damages and better roughness. However, ultra-thinned Si samples have the almost same hardness as a bulk Si wafer.
Optimum Design of Bonding Pads for Prevention of Passivation Damage in Semiconductor Devices Utilizing Lead-on-Chip (LOC) Die Attach Technique
Lee, Seong-Min ; Kim, Chong-Bum ;
Journal of the Microelectronics and Packaging Society, volume 15, issue 2, 2008, Pages 69~73
This article shows that the susceptibility of the device pattern to thermal stress-induced damage has a strong dependence on its proximity to the device comer in semiconductor devices utilizing lead-on-chip (LOC) die attach technique. The result, as explained based on numerical calculation and experiment, indicateds that the stress-driven damage potential of the passivation layer is the highest at the device comer. Thus, the bonding pads, which are very susceptible to passivation damage, should be designed to be located along the central region rather than the peripheral region of the device.