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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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Journal of the Microelectronics and Packaging Society
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Journal DOI :
The Korean Microelectronics and Packaging Society
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Volume & Issues
Volume 17, Issue 4 - Dec 2010
Volume 17, Issue 3 - Sep 2010
Volume 17, Issue 2 - Jun 2010
Volume 17, Issue 1 - Mar 2010
Selecting the target year
Ultimate Heterogeneous Integration Technology for Super-Chip
Lee, Kang-Wook ;
Journal of the Microelectronics and Packaging Society, volume 17, issue 4, 2010, Pages 1~9
Three-dimensional (3-D) integration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip to form highly integrated micro-nano systems. Since CMOS device scaling has stalled, 3D integration technology allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. The potential benefits of 3D integration can vary depending on approach; increased multifunctionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. It is expected that the semiconductor industry's paradiam will be shift to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D based technologies in highly integrated systems. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of IT-NT-BT systems. This paper attempts to introduce new 3D integration technologies of the chip self-assembling stacking and 3D heterogeneous opto-electronics integration for realizng the super-chip.
Electro-migration Phenomenon in Flip-chip Packages
Lee, Ki-Ju ; Kim, Keun-Soo ; Suganuma, Katsuaki ;
Journal of the Microelectronics and Packaging Society, volume 17, issue 4, 2010, Pages 11~17
The electromigration phenomenon in lead-free flip-chip solder joint has been one of the serious problems. To understand the mechanism of this phenomenon, the crystallographic orientation of Sn grain in the Sn-Ag-Cu solder bump has been analyzed. Different time to failure and different microstructural changes were observed in the all test vehicle and bumps, respectively. Fast failure and serious dissolution of Cu electrode was observed when the c-axis of Sn grain parallel to electron flow. On the contrary of this, slight microstructural changes were observed when the c-axis of Sn perpendicular to electron flow. In addition, underfill could enhance the electromigration reliability to prevent the deformation of solder bump during EM test.
Accelerated Degradation Stress of High Power Phosphor Converted LED Package
Chan, Sung-Il ; Jang, Joong-Soon ;
Journal of the Microelectronics and Packaging Society, volume 17, issue 4, 2010, Pages 19~26
We found that saturated water vapor pressure is the most dominant stress factor for the degradation phenomenon in the package for high-power phosphor-converted white light emitting diode (high power LED). Also, we proved that saturated water vapor pressure is effective acceleration stress of LED package degradation from an acceleration life test. Test conditions were
, 100% R.H., and max. 168 h storage with and without 350 mA. The accelerating tests in both conditions cause optical power loss, reduction of spectrum intensity, device leakage current, and thermal resistance in the package. Also, dark brown color and pore induced by hygro-mechanical stress partially contribute to the degradation of LED package. From these results, we have known that the saturated water vapor pressure stress is adequate as the acceleration stress for shortening life test time of LED packages.
A Method for Reducing the Number of Metal Layers for Embedded LSI Package
Ohshima, Daisuke ; Mori, Kentaro ; Nakashima, Yoshiki ; Kikuchi, Katsumi ; Yamamichi, Shintaro ;
Journal of the Microelectronics and Packaging Society, volume 17, issue 4, 2010, Pages 27~33
We have successfully demonstrated a high-pin-count and thin embedded-LSI package to realize next generation's mobile terminals. The following three design key points were applied: (i) Using Cu posts, (ii) Using the coreless structure, (iii) Using a Cu plate as the ground plane. In order to quantitatively determine the contribution of the three points, the five-stage process for reducing the number of metal layers is described by means of the electrical simulation. The point-(i) and (ii) are effective from the viewpoint of the power integrity (PI); that is, these points play important roles in reducing the number of metal layers, and especially the point-(ii) contributes at least twice as the point-(i). The point-(iii) is not effective in the PI, but has a few effects on the signal integrity (SI). For reducing the number of metal layers, we should, at first, pay attention whether the PI characteristics fulfill the specification, and then we should confirm the SI characteristics.
Evaluation on Reliability of High Temperature Lead-free Solder for Automotive Electronics
Ko, Yong-Ho ; Yoo, Se-Hoon ; Lee, Chang-Woo ;
Journal of the Microelectronics and Packaging Society, volume 17, issue 4, 2010, Pages 35~40
In this study, the reliability of thermal shock, thermal cycle, and complex vibration test at high temperature were examined for 3 types of lead-free solder alloys, Sn-3.5Ag, Sn-0.7Cu and Sn-5.0Sb. For the reliability test, daisychained BGA chips with ENIG-finished Cu pad was assembled with the three lead-free solders on OSP-finished PCBs. Among the 3 types solder alloys, Sn-3.5Ag solder alloy showed the highest degradation rate of electrical resistance and joint strength. On the other hand, Sn-0.7Cu solder alloy had high stability after the reliability tests.
Encapsulation of an 2-methyl Imidazole Curing Accelerator for the Extended Pot Life of Anisotropic Conductive Pastes (ACPs)
Kim, Ju-Hyung ; Kim, Jun-Ki ; Hyun, Chang-Yong ; Lee, Jong-Hyun ;
Journal of the Microelectronics and Packaging Society, volume 17, issue 4, 2010, Pages 41~48
To improve the pot life of one-part in-house anisotropic conductive paste (ACP) formulations, 2-methyl imidazole curing accelerator powders were encapsulated with five agents. Through measuring the melting point of the five agents using DSC, it was confirmed that a encapsulation process with liquid-state agents is possible. Viscosity of ACP formulations containing the encapsulated imidazole powders was measured as a function of storage time from viscosity measurements. As a result, pot life of the formulations containing imidazole powders encapsulated with stearic acid and carnauba wax was improved, and these formulations indicated similar curing behaviors to a basic formulation containing rare imidazole. However, the bondlines made of these formulations exhibited low average shear strength values of about 37% level in comparison with the basic formulation.
Numerical Study of Warpage and Stress for the Ultra Thin Package
Song, Cha-Gyu ; Choa, Sung-Hoon ;
Journal of the Microelectronics and Packaging Society, volume 17, issue 4, 2010, Pages 49~60
Semiconductor packages are increasingly moving toward miniaturization, lighter and high performance. Futhermore, packages become thinner. Thin packages will generate serious reliability problems such as warpage, crack and other failures. Reliability problems are mainly caused by the CTE mismatch of various package materials. Therefore, proper selection of the package materials and geometrical optimization is very important for controlling the warpage and the stress of the package. In this study, we investigated the characteristics of the warpage and the stress of several packages currently used in mobile devices such as CABGA, fcSCP, SCSP, and MCP. Warpage and stress distribution are analyzed by the finite element simulation. Key material properties which affect the warpage of package are investigated such as the elastic moduli, CTEs of EMC molding and the substrate. Geometrical effects are also investigated including the thickness or size of EMC molding, silicon die and substrate. The simulation results indicate that the most influential factors on warpage are EMC molding thickness, CTE of EMC, elastic modulus of the substrate. Simulation results show that warpage is the largest for SCSP. In order to reduce the warpage, DOE optimization is performed, and the optimization results show that warpage of SCSP becomes
Cu Thickness Effects on Bonding Characteristics in Cu-Cu Direct Bonds
Kim, Jae-Won ; Jeong, Myeong-Hyeok ; Carmak, Erkan ; Kim, Bioh ; Matthias, Thorsten ; Lee, Hak-Joo ; Hyun, Seung-Min ; Park, Young-Bae ;
Journal of the Microelectronics and Packaging Society, volume 17, issue 4, 2010, Pages 61~66
Cu-Cu thermo-compression bonding process was successfully developed as functions of the deposited Cu thickness and
forming gas annealing conditions before and after bonding step in order to find the low temperature bonding conditions of 3-D integrated technology where the interfacial toughness was measured by 4-point bending test. Pre-annealing with
is effective to achieve enough interfacial adhesion energy irrespective of Cu film thickness. Successful Cu-Cu bonding process achieved in this study results in delamination at
interface rather than Cu/Cu interface.
Design Optimization of Ball Grid Array Packaging by the Taguchi Method
Kim, Yeong-K. ; Kim, Jae-chang ; Choi, Joo-Ho ;
Journal of the Microelectronics and Packaging Society, volume 17, issue 4, 2010, Pages 67~72
In this paper, a design optimization of ball grid array packaging geometry is studied based on the Taguchi method, which allowed robust design by considering the variance of the input parameters during the optimization process. Molding compound and substrate were modeled as viscoelastic, and finite element analyses were performed to calculate the strain energy densities of the eutectic solder balls. Six quality factors of the dimensions of the packaging geometry were chosen as control factors. After performing noise experiments to determine the dominant factors, main experiments were conducted to find the optimum packaging geometry. Then the strain energy densities between the original and optimized geometries were compared. It was found that the effects of the packaging geometry on the solder ball reliability were significant, and more than 40% of the strain energy density was reduced by the geometry optimization.
Experimental investigation of Scalability of DDR DRAM packages
Crisp, R. ;
Journal of the Microelectronics and Packaging Society, volume 17, issue 4, 2010, Pages 73~76
A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded
. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.
Effects of Evaporation Processes and a Reduction Annealing on Thermoelectric Properties of the Sb-Te Thin Films
Bae, Jae-Man ; Kim, Min-Young ; Oh, Tae-Sung ;
Journal of the Microelectronics and Packaging Society, volume 17, issue 4, 2010, Pages 77~82
Effects of evaporation processes and a reduction annealing on thermoelectric properties of the Sb-Te thin films prepared by thermal evaporation have been investigated. The thin film evaporated by using the powders formed by crushing a
ingot as an evaporation source exhibited a power factor of
. The thin film processed by evaporation of the mixed powders of Sb and Te as an evaporation source showed a power factor of
. The thin film fabricated by coevaporation of Sb and Te dual evaporation sources possessed a power factor of
. With a reduction annealing at
for 2 hrs, the power factors of the films evaporated by using the
ingot-crushed powders and coevaporated with Sb and Te dual evaporation sources were remarkably improved to
Electrodeposition of Permalloy-Silica Composite Coating
Jung, Myung-Won ; Kim, Jong-Hoon ; Lee, Heung-Yeol ; Lee, Jae-Ho ;
Journal of the Microelectronics and Packaging Society, volume 17, issue 4, 2010, Pages 83~88
The composite electroplating is accomplished by adding inert materials during the electroplating. Permalloy is the term for Ni-Fe alloy and it is used for industrial applications due to its high magnetic permeability. Microhardness for microdevices is enhanced after composite coating and it increases the life cycle. However, the hydroxyl group on the silica makes their surface susceptible to moisture and it causes the silica nanoparticles to be agglomerated in the aqueous solution. The agglomeration problem causes poor dispersion which eventually interrupts uniform deposition of silica nanoparticles. In this study, the dispersion of silica nanoparticles in the permalloy electroplated layer is reported with variation of additives and sonication time. Longer sonication period guaranteed better silica nanopowder dispersion and sonication period also influenced on composition of deposits. The amount of silica nanopowder codeposition and surface morphologies were influenced with variation of additives. In alkaline bath, smooth surface morphology and relatively high contents of silica nanopowder codeposition were obtained with addition of sodium lauryl sulfate.
Thermoelectric Properties of Bi-Te Thin Films Processed by Coevaporation
Choi, Young-Nam ; Kim, Min-Young ; Oh, Tae-Sung ;
Journal of the Microelectronics and Packaging Society, volume 17, issue 4, 2010, Pages 89~94
Bi-Te films were processed by coevaporation of Bi and Te dual sources with variations of the mole ratio of the Bi and Te evaporation sources, and thermoelectric properties of the coevaporated Bi-Te films were characterized. The coevaporated Bi-Te films were n-type semiconductors and exhibited Seebeck coefficients of
. The Terich Bi-Te film, processed with Bi and Te dual sources of 30 mol% Bi : 70 mol% Te ratio, exhibited a power factor of
. On the other hand, a power factor of
was obtained for the Bi-rich film coevaporated using Bi and Te dual sources of 90 mol% Bi : 10 mol% Te ratio.
Variation of Thermal Resistance of LED Module Embedded by Thermal Via
Shin, Hyeong-Won ; Lee, Hyo-Soo ; Bang, Jae-Oh ; Yoo, Se-Hoon ; Jung, Seung-Boo ; Kim, Kang-Dong ;
Journal of the Microelectronics and Packaging Society, volume 17, issue 4, 2010, Pages 95~100
LED (Light Emitting Diode) is 85% of the applied energy is converted into heat that is already well known. Lately, LED chips increasing the capacity as result delivered to increase the heat of the LED products and module that directly related to life span and degradation. Thus, in industry the high-power LED chip to control the heat generated during the course of the study and the existing aluminum, copper adhesives, and uses MLC (Metal clad laminate) structures using low-cost FR4 and copper CCL (Copper Clad Laminate) to reduce costs by changing to a study being carried out. In this study, using low-cost CCL Class, mounted 1W LED chip to analyze changes in the thermal resistance. In addition, heat dissipation in the CCL to facilitate a variety of thermal via design outside of the heat generated by the LED chip to control and facilitate the optimal structure of the heat dissipation is suggested.