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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
Journal of the Microelectronics and Packaging Society
Journal Basic Information
Journal DOI :
The Korean Microelectronics and Packaging Society
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Volume & Issues
Volume 19, Issue 4 - Dec 2012
Volume 19, Issue 3 - Sep 2012
Volume 19, Issue 2 - Jun 2012
Volume 19, Issue 1 - Mar 2012
Selecting the target year
Application of Plating Simulation for PCB and Pakaging Process
Lee, Kyu Hwan ;
Journal of the Microelectronics and Packaging Society, volume 19, issue 3, 2012, Pages 1~7
DOI : 10.6117/kmeps.2012.19.3.001
Electroplating technology is widely used in semiconductor microelectronic industry. With the development of semiconductor integrated circuit to high density and light-small scale, Extremely high quality and plated uniformity of the deposited metals are needed. Simulation technique can help to obtain better plating results. Although a few plating simulation softwares have been commercialized, plating simulation is not widely prevalent in Korea. In this paper, principle of electroplating and mathematical modeling of plating simulation are discussed. Also introduced are some cases enhancing plating thickness uniformity on leadframe, PCB and wafer by using plating simulation.
Interconnect Process Technology for High Power Delivery and Distribution
Oh, Keong-Hwan ; Ma, Jun-Sung ; Kim, Sungdong ; Kim, Sarah Eunkyung ;
Journal of the Microelectronics and Packaging Society, volume 19, issue 3, 2012, Pages 9~14
DOI : 10.6117/kmeps.2012.19.3.009
Robust power delivery and distribution are considered one of the major challenges in electronic devices today. As a technology develops (i.e. frequency and complexity, increase and size decreases), both power density and power supply noise increase, and voltage supply margin decreases. In addition, thermal problem is induced due to high power and poor power distribution. Until now most of studies to improve power delivery and distribution have been focused on device circuit or system architecture designs. Interconnect process technologies to resolve power delivery issues have not greatly been explored so far, but recently it becomes of great interest as power increases and voltage specification decreases in a smaller chip size.
The Chip Bonding Technology on Flexible Substrate by Using Micro Lead-free Solder Bump
Kim, Min-Su ; Ko, Yong-Ho ; Bang, Jung-Hwan ; Lee, Chang-Woo ;
Journal of the Microelectronics and Packaging Society, volume 19, issue 3, 2012, Pages 15~20
DOI : 10.6117/kmeps.2012.19.3.015
In electronics industry, the coming electronic devices will be expected to be high integration and convergence electronics. And also, it will be expected that the coming electronics will be flexible, bendable and wearable electronics. Therefore, the demands and interests of bonding technology between flexible substrate and chip for mobile electronics, e-paper etc. have been increased because of weight and flexibility of flexible substrate. Considering fine pitch for high density and thermal damage of flexible substrate during bonding process, the micro solder bump technology for high density and low temperature bonding process for reducing thermal damage will be required. In this study, we researched on bonding technology of chip and flexible substrate by using 25um Cu pillar bumps and Sn-Bi solder bumps were formed by electroplating. From the our study, we suggest technology on Cu pillar bump formation, Sn-Bi solder bump formation, and bonding process of chip and flexible substrate for the coming electronics.
Electrically Programmable Fuse - Application, Program and Reliability
Kim, Deok-Kee ;
Journal of the Microelectronics and Packaging Society, volume 19, issue 3, 2012, Pages 21~30
DOI : 10.6117/kmeps.2012.19.3.021
Technology trend and application of laser fuse, anti-fuse, and eFUSE as well as the structure, programming mechanism, and reliability of eFUSE have been reviewed. In order to ensure eFUSE reliability in the field, a sensing circuit trip point consistent with the fuse resistance distribution, process variation, and device degradation in the circuit such as hot carrier or NBTI, as well as fuse resistance reliability must be considered to optimize and define a reliable fuse programming window.
Reliability of High Temperature and Vibration in Sn3.5Ag and Sn0.7Cu Lead-free Solders
Ko, Yong-Ho ; Kim, Taek-Soo ; Lee, Young-Kyu ; Yoo, Sehoo ; Lee, Chang-Woo ;
Journal of the Microelectronics and Packaging Society, volume 19, issue 3, 2012, Pages 31~36
DOI : 10.6117/kmeps.2012.19.3.031
In this study, the complex vibration reliability of Sn-3.5Ag and Sn-0.7Cu having a high melting temperature was investigated. For manufacturing of BGA test samples, Sn-3.5Ag and Sn-0.7Cu balls were joined on BGA chips finished by ENIG and the chips were mounted on PCB finished OSP by using reflow process. For measuring of resistance change during complex vibration test, daisy chain was formed in the test board. From the results of resistance change and shear strength change, the reliability of two solder balls was compared and evaluated. During complex vibration for 120 hours, Sn-0.7Cu solder was more stable than Sn-3.5Ag solder in complex vibration test.
Ti/Cu CMP process for wafer level 3D integration
Kim, Eunsol ; Lee, Minjae ; Kim, Sungdong ; Kim, Sarah Eunkyung ;
Journal of the Microelectronics and Packaging Society, volume 19, issue 3, 2012, Pages 37~41
DOI : 10.6117/kmeps.2012.19.3.037
The wafer level stacking with Cu-to-Cu bonding becomes an important technology for high density DRAM stacking, high performance logic stacking, or heterogeneous chip stacking. Cu CMP becomes one of key processes to be developed for optimized Cu bonding process. For the ultra low-k dielectrics used in the advanced logic applications, Ti barrier has been preferred due to its good compatibility with porous ultra low-K dielectrics. But since Ti is electrochemically reactive to Cu CMP slurries, it leads to a new challenge to Cu CMP. In this study Ti barrier/Cu interconnection structure has been investigated for the wafer level 3D integration. Cu CMP wafers have been fabricated by a damascene process and two types of slurry were compared. The slurry selectivity to
and Ti and removal rate were measured. The effect of metal line width and metal density were evaluated.
Error Analysis for Microwave Permittivity Measurement using Post Resonator Method
Cho, Mun-Seong ; Lim, Donggun ; Park, Jae-Hwan ; Park, Jae-Gwan ;
Journal of the Microelectronics and Packaging Society, volume 19, issue 3, 2012, Pages 43~48
DOI : 10.6117/kmeps.2012.19.3.043
Errors of relative permittivity calculation caused by the variation of sample aspect ratio (diameter/height) and measuring geometry were analyzed by computer simulation and measurement. Firstly, the
spectrum of the sample (permittivity 38) was simulated in the post resonator measuring apparatus by HFSS simulation. Then, the relative permittivity was calculated from the
mode resonant frequency. The relative permittivity varied by ca. 0.3% with sample aspect ratio variation (D/H
Analysis on the Thermal Deformation of Flip-chip Bump Layer by the IMC`s Implication
Lee, Tae Kyoung ; Kim, Dong Min ; Jun, Ho In ; Huh, Seok-Hwan ; Jeong, Myung Young ;
Journal of the Microelectronics and Packaging Society, volume 19, issue 3, 2012, Pages 49~56
DOI : 10.6117/kmeps.2012.19.3.049
Recently, by the trends of electronic package to be smaller, thinner and more integrative, fine bump is required. but It can result in the electrical short by reduced cross-section of UBM and diameter of bump. Especially, the formation of IMCs and KV can have a significant affects about electrical and mechanical properties. In this paper, we analyzed the thermal deformation of flip-chip bump by using FEM. Through Thermal Cycling Test (TCT) of flip-chip package, We analyzed the properties of the thermal deformation. and We confirmed that the thermal deformation of the bump can have a significant impact on the driving system. So we selected IMCs thickness and bump diameter as variable which is expected to have implications for characteristics of thermal deformation. and we performed analysis of temperature, thermal stress and thermal deformation. Then we investigated the cause of the IMC`s effects.
Numerical Analysis on the Design Variables and Thickness Deviation Effects on Warpage of Substrate for FCCSP
Cho, Seunghyun ; Jung, Hunil ; Bae, Onecheol ;
Journal of the Microelectronics and Packaging Society, volume 19, issue 3, 2012, Pages 57~62
DOI : 10.6117/kmeps.2012.19.3.057
In this paper, numerical analysis by finite element method, parameter design by the Taguchi method and ANOVA method were used to analyze about effect of design deviations and thickness variations on warpage of FCCSP substrate. Based on the computed results, it was known that core material in substrate was the most determining deviation for reducing warpage. Solder resist, prepreg and circuit layer were insignificant effect on warpage relatively. But these results meant not thickness effect was little importance but mechanical properties of core material were very effective. Warpage decreased as Solder resist and circuit layer thickness decreased but effect of prepreg thickness was conversely. Also, these results showed substrate warpage would be increased to maximum 40% as thickness deviation combination. It meant warpage was affected by thickness tolerance under manufacturing process even if it were met quality requirements. Threfore, it was strongly recommended that substrate thickness deviation should be optimized and controlled precisely to reduce warpage in manufacturing process.
Adhesion Reliability Enhancement of Silicon/Epoxy/Polyimide Interfaces for Flexible Electronics
Kim, Sanwi ; Kim, Taek-Soo ;
Journal of the Microelectronics and Packaging Society, volume 19, issue 3, 2012, Pages 63~69
DOI : 10.6117/kmeps.2012.19.3.063
Adhesion and mechanical reliability of silicon/epoxy/polyimide interfaces are critical issues for flexible electronics. Bonds between these interfaces are mainly hydrogen bonds, so their adhesion is weaker than cohesive fracture toughness and vulnerable to moisture. In order to enhance adhesion and suppress moisture-assisted debonding, UV/Ozone treatment and innovative sol-gel derived hybrid layers were applied to silicon/epoxy/polyimide interfaces. The fracture energy and subcritical crack growth rate were measured by using a double cantilever beam (DCB) fracture mechanics test. Results showed that UV/Ozone treatment increased the adhesion, but was not effective for improving reliability against humidity. However, by applying sol-gel derived hybrid layers, adhesion increase as well as suppresion of moisture-assisted cracking were achieved.
Chip Interconnection Process for Smart Fabrics Using Flip-chip Bonding of SnBi Solder
Choi, J.Y. ; Park, D.H. ; Oh, T.S. ;
Journal of the Microelectronics and Packaging Society, volume 19, issue 3, 2012, Pages 71~76
DOI : 10.6117/kmeps.2012.19.3.071
A chip interconnection technology for smart fabrics was investigated by using flip-chip bonding of SnBi low-temperature solder. A fabric substrate with a Cu leadframe could be successfully fabricated with transferring a Cu leadframe from a carrier film to a fabric by hot-pressing at
. A chip specimen with SnBi solder bumps was formed by screen printing of SnBi solder paste and was connected to the Cu leadframe of the fabric substrate by flip-chip bonding at
for 60 sec. The average contact resistance of the SnBi flip-chip joint of the smart fabric was measured as
The Study on Chip Surface Treatment for Embedded PCB
Jeon, Byung-Sub ; Park, Se-Hoon ; Kim, Young-Ho ; Kim, Jun-Cheol ; Jung, Seung-Boo ;
Journal of the Microelectronics and Packaging Society, volume 19, issue 3, 2012, Pages 77~82
DOI : 10.6117/kmeps.2012.19.3.077
In this paper, the research of IC embedded PCB process is carried out. For embedding chips into PCB, solder-balls on chips were etched out and ABF(Ajinomoto Build-ip Film), prepreg and Cu foil was laminated on that to fabricate 6 layer build-up board. The chip of which solder ball was removed was successfully interconnected with PCB by laser drilling and Cu plating. However, de-lamination phenomenon occurred between chip surface and ABF during reflow and thermal shock. To solve this problem, de-smear and plasma treatment was applied to PI(polyimide) passivation layer on chip surface to improve the surface roughness. The properties of chip surface(PI) was investigated in terms of AFM(Atomic Force Micrometer), SEM and XPS (X-ray Photoelectron Spectroscopy). As results, nano-size anchor was evenly formed on PI surface when plasma treatment was combined with de-smear(NaOH+KMnO4) process and it improved thermal shock reliability (
-10sec solder floating).