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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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Journal of the Microelectronics and Packaging Society
Journal Basic Information
Journal DOI :
The Korean Microelectronics and Packaging Society
Editor in Chief :
Volume & Issues
Volume 21, Issue 4 - Dec 2014
Volume 21, Issue 3 - Sep 2014
Volume 21, Issue 2 - Jun 2014
Volume 21, Issue 1 - Mar 2014
Selecting the target year
Technology of Flexible Transparent Conductive Electrode for Flexible Electronic Devices
Kim, Joo-Hyun ; Chon, Min-Woo ; Choa, Sung-Hoon ;
Journal of the Microelectronics and Packaging Society, volume 21, issue 2, 2014, Pages 1~11
DOI : 10.6117/kmeps.2014.21.2.001
Flexible transparent conductive electrodes (TCEs) have recently attracted a great deal of attention owing to rapid advances in flexible electronic devices, such as flexible displays, flexible photovoltanics, and e-papers. As the performance and reliability of flexible electronics are critically affected by the quality of TCE films, it is imperative to develop TCE films with low resistivity and high transparency as well as high flexibility. Indium tin oxide (ITO) has been the most dominant transparent conducting material due to its high optical transparency and electrical conductivity. However, ITO is susceptible to cracking and delamination when it is bent or deformed. Therefore, various types of flexible TCEs, such as carbon nanotube, conducting polymers, graphene, metal mesh, Ag nanowires (NWs), and metal mesh have been extensively investigated. Among several options to replace ITO film, Ag NWs and metal mesh have been suggested as the promising candidate for flexible TCEs. In this paper, we focused on Ag NWs and metal mesh, and summarized the current development status of Ag NWs and metal mesh. The several critical issues such as high contact resistance and haze are discussed, and newly developed technologies to resolve these issues are also presented. In particular, the flexibility and durability of Ag NWs and metal mesh was compared with ITO electrode.
Overview on Thermal Management Technology for High Power Device Packaging
Kim, Kwang-Seok ; Choi, Don-Hyun ; Jung, Seung-Boo ;
Journal of the Microelectronics and Packaging Society, volume 21, issue 2, 2014, Pages 13~21
DOI : 10.6117/kmeps.2014.21.2.013
Technology for high power devices has made impressive progress in increasing the current density of power semiconductor, system module, and design optimization, which realize high power systems with heterogeneous functional integration. Depending on the performance development of high power semiconductor, packaging technology of high power device is urgently required for efficiency improvement of the device. Power device packaging must provide superior thermal management due to high operating temperature of power modules. Here we, therefore, review critical challenges of typical power electronics packaging today including core assembly processes, component materials, and reliability evaluation regulations.
A study on Electrical Characteristic and Thermal Shock Property of TSV for 3-Dimensional Packaging
Jeong, Il Ho ; Kee, Se Ho ; Jung, Jae Pil ;
Journal of the Microelectronics and Packaging Society, volume 21, issue 2, 2014, Pages 23~29
DOI : 10.6117/kmeps.2014.21.2.023
Less power consumption, lower cost, smaller size and more functionality are the increasing demands for consumer electronic devices. The three dimensional(3-D) TSV packaging technology is the potential solution to meet this requirement because it can supply short vertical interconnects and high input/output(I/O) counts. Cu(Copper) has usually been chosen to fill the TSV because of its high conductivity, low cost and good compatibility with the multilayer interconnects process. However, the CTE mismatch and Cu ion drift under thermal stress can raise reliability issues. This study discribe the thermal stress reliability trend for successful implementation of 3-D packaging.
Thickness-dependent Electrical, Structural, and Optical Properties of ALD-grown ZnO Films
Choi, Yong-June ; Kang, Kyung-Mun ; Park, Hyung-Ho ;
Journal of the Microelectronics and Packaging Society, volume 21, issue 2, 2014, Pages 31~35
DOI : 10.6117/kmeps.2014.21.2.031
The thickness dependent electrical, structural, and optical properties of ZnO films grown by atomic layer deposition (ALD) at various growth temperatures were investigated. In order to deposit ZnO films, diethylzinc and deionized water were used as metal precursor and reactant, respectively. ALD process window was found at the growth temperature range from
with a growth rate of about
. The electrical properties were studied by using van der Pauw method with Hall effect measurement. The structural and optical properties of ZnO films were analyzed by using X-ray diffraction, field emission scanning electron microscopy, and UV-visible spectrometry as a function of thickness values of ZnO films, which were selected by the lowest electrical resistivity. Finally, the figure of merit of ZnO films could be estimated as a function of the film thickness. As a result, this investigation of thickness dependent electrical, structural, and optical properties of ZnO films can provide proper information when applying to optoelectronic devices, such as organic light-emitting diodes and solar cells.
Study of micro flip-chip process using ABL bumps
Ma, Junsung ; Kim, Sungdong ; Kim, Sarah Eunkyung ;
Journal of the Microelectronics and Packaging Society, volume 21, issue 2, 2014, Pages 37~41
DOI : 10.6117/kmeps.2014.21.2.037
One of the important developments in next generation electronic devices is the technology for power delivery and heat dissipation. In this study, the Cu-to-Cu flip chip bonding process was evaluated using the square ABL power bumps and circular I/O bumps. The difference in bump height after Cu electroplating followed by CMP process was about
and the bump height after Cu electroplating only was about
. Also, the height of ABL bumps was higher than I/O bumps. The degree of Cu bump planarization and Cu bump height uniformity within a die affected significantly on the misalignment and bonding quality of Cu-to-Cu flip chip bonding process. To utilize Cu-to-Cu flip chip bonding with ABL bumps, both bump planarization and within-die bump height control are required.
Thermal Analysis of 3D package using TSV Interposer
Suh, Il-Woong ; Lee, Mi-Kyoung ; Kim, Ju-Hyun ; Choa, Sung-Hoon ;
Journal of the Microelectronics and Packaging Society, volume 21, issue 2, 2014, Pages 43~51
DOI : 10.6117/kmeps.2014.21.2.043
In 3-dimensional (3D) integrated package, thermal management is one of the critical issues due to the high heat flux generated by stacked multi-functional chips in miniature packages. In this study, we used numerical simulation method to analyze the thermal behaviors, and investigated the thermal issues of 3D package using TSV (through-silicon-via) technology for mobile application. The 3D integrated package consists of up to 8 TSV memory chips and one logic chip with a interposer which has regularly embedded TSVs. Thermal performances and characteristics of glass and silicon interposers were compared. Thermal characteristics of logic and memory chips are also investigated. The effects of numbers of the stacked chip, size of the interposer and TSV via on the thermal behavior of 3D package were investigated. Numerical analysis of the junction temperature, thermal resistance, and heat flux for 3D TSV package was performed under normal operating and high performance operation conditions, respectively. Based on the simulation results, we proposed an effective integration scheme of the memory and logic chips to minimize the temperature rise of the package. The results will be useful of design optimization and provide a thermal design guideline for reliable and high performance 3D TSV package.
Laser Drilling of High-Density Through Glass Vias (TGVs) for 2.5D and 3D Packaging
Delmdahl, Ralph ; Paetzel, Rainer ;
Journal of the Microelectronics and Packaging Society, volume 21, issue 2, 2014, Pages 53~57
DOI : 10.6117/kmeps.2014.21.2.053
Thin glass (< 100 microns) is a promising material from which advanced interposers for high density electrical interconnects for 2.5D chip packaging can be produced. But thin glass is extremely brittle, so mechanical micromachining to create through glass vias (TGVs) is particularly challenging. In this article we show how laser processing using deep UV excimer lasers at a wavelength of 193 nm provides a viable solution capable of drilling dense patterns of TGVs with high hole counts. Based on mask illumination, this method supports parallel drilling of up over 1,000 through vias in 30 to
thin glass sheets. (We also briefly discuss that ultrafast lasers are an excellent alternative for laser drilling of TGVs at lower pattern densities.) We present data showing that this process can deliver the requisite hole quality and can readily achieve future-proof TGV diameters as small
together with a corresponding reduction in pitch size.
High-Yield Etching-Free Transfer of Graphene: A Fracture Mechanics Approach
Yoon, Taeshik ; Jo, Woo Sung ; Kim, Taek-Soo ;
Journal of the Microelectronics and Packaging Society, volume 21, issue 2, 2014, Pages 59~64
DOI : 10.6117/kmeps.2014.21.2.059
Transfer is the critical issue of producing high-quality and scalable graphene electronic devices. However, conventional transfer processes require the removal of an underlying metal layer by wet etching process, which induces significant economic and environmental problems. We propose the etching-free mechanical releasing of graphene using polymer adhesives. A fracture mechanics approach was introduced to understand the releasing mechanism and ensure highyield process. It is shown that the thickness of adhesive and target substrate affect the transferability of graphene. Based on experimental and fracture mechanics simulation results, we further observed that compliant adhesives can reduce the adhesive stress during the transfer, which also enhances the success probability of graphene transfer.
Warpage Characteristics Analysis for Top Packages of Thin Package-on-Packages with Progress of Their Process Steps
Park, D.H. ; Jung, D.M. ; Oh, T.S. ;
Journal of the Microelectronics and Packaging Society, volume 21, issue 2, 2014, Pages 65~70
DOI : 10.6117/kmeps.2014.21.2.065
Warpage of top packages to form thin package-on-packages was measured with progress of their process steps such as PCB substrate itself, chip bonding, and epoxy molding. The
-thick PCB substrate exhibited a warpage of
. The specimen formed by mounting a
-thick Si chip to such a PCB using a die attach film exhibited the warpage of
, which was similar to that of the PCB itself. On the other hand, the specimen fabricated by flip chip bonding of a
-thick chip to such a PCB possessed the warpage of
, which was significantly different from the warpage of the PCB. After epoxy molding, the specimens processed by die attach bonding and flip chip bonding exhibited warpages of
SiC based Technology for High Power Electronics and Packaging Applications
Sharma, Ashutosh ; Lee, Soon Jae ; Jang, Young Joo ; Jung, Jae Pil ;
Journal of the Microelectronics and Packaging Society, volume 21, issue 2, 2014, Pages 71~78
DOI : 10.6117/kmeps.2014.21.2.071
Silicon has been most widely used semiconductor material for power electronic systems. However, Si-based power devices have attained their working limits and there are a lot of efforts for alternative Si-based power devices for better performance. Advances in power electronics have improved the efficiency, size, weight and materials cost. New wide band gap materials such as SiC have now been introduced for high power applications. SiC power devices have been evolved from lab scale to a viable alternative to Si electronics in high-efficiency and high-power density applications. In this article, the potential impact of SiC devices for power applications will be discussed along with their Si counterpart in terms of higher switching performance, higher voltages and higher power density. The recent progress in the development of high voltage power semiconductor devices is reviewed. Future trends in device development and industrialization are also addressed.
Fabrication of a Ultrathin Ag Film on a Thin Cu Film by Low-Temperature Immersion Plating in an Grycol-Based Solution
Kim, Ji Hwan ; Cho, Young Hak ; Lee, Jong-Hyun ;
Journal of the Microelectronics and Packaging Society, volume 21, issue 2, 2014, Pages 79~84
DOI : 10.6117/kmeps.2014.21.2.079
To investigate the plating properties of a diethylene glycol-based Ag immersion plating solution containing citric acid, silver immersion plating was performed in a range from room temperature to
using sputtered Cu specimens. The used Cu specimens possessed surface structure with large numbers of pinholes which were created with over-acid etching. The Ag immersion plating performed at
exhibited that the pinholes and copper surface were completely filled with Ag just after 5 min mainly due to galvanic displacement reaction, indicating the best plating properties. Subsequently, the surface morphology of Ag-coated Cu became rougher as the plating time increased to 30 min because of the deposition of silver nanoparticles created by chemical reduction in the solution. The specimen that its overall surface was covered with silver indicated the start of oxidation at temperature higher than around
in air as compared with pure Cu, indicating enhanced anti-oxidation properties.
A study on the Nano Wire Grid Polarizer Film by Magnetic Soft Mold
Jo, Sang-Uk ; Chang, Sunghwan ; Choi, Doo-Sun ; Huh, Seok-Hwan ; Jeong, Myung Yung ;
Journal of the Microelectronics and Packaging Society, volume 21, issue 2, 2014, Pages 85~89
DOI : 10.6117/kmeps.2014.21.2.085
We propose the new fabrication method of a 70 nm half-pitch wire grid polarizer with high performance using magnetic soft mold. The device is a form of aluminium gratings on a PET(Polyethylene phthalate) substrate whose size of
is compatible with a TFT_LCD(Tin Flat Transistor Liquid Crystal Display) panel. A magnetic soft mold with a pitch of 70 nm is fabricated using two-step replication method. As a result, we get a NWGP pattern which has 70.39 nm line width, 64.76 nm depth, 140.78 nm pitch, on substrate. The maximum and minimum transmittances of the NWGP at 800 nm are 75% and 10%, respectively. This work demonstrates a unique cost-effective solution for nanopatterning requirements in consumer electronics components.
High-Speed Shear Test Characterization of Sn-Ag-Cu-In Quaternary Solder Joint
Kim, Ju-Hyung ; Hyun, Chang-Yong ;
Journal of the Microelectronics and Packaging Society, volume 21, issue 2, 2014, Pages 91~97
DOI : 10.6117/kmeps.2014.21.2.091
With Pb-free solder joints containing Sn-Ag-Cu-based ternary alloys (Sn-1.0 wt.%Ag-0.5Cu and Sn-4.0Ag-0.5Cu) and Sn-Ag-Cu-In-based quaternary alloys (Sn-1.0Ag-0.5Cu-1.0In, Sn-1.2Ag-0.5Cu-0.4In, Sn-1.2Ag-0.5Cu-0.6In, and Sn-1.2Ag-0.7Cu-0.4In), fracture-mode change, shear strengths, and fracture energies were observed and measured under a high-speed shear test of 500 mm/s. The samples in each composition were prepared with as-reflowed ones or solid-aged ones at
to 500 h. As a result, it was observed that ductile or quasi-ductile fracture modes occurs in the most of Sn-Ag-Cu-In samples. The happening frequency of a quasi-ductile fracture mode showed that the Sn-Ag-Cu-In joints possessed ductile fracture properties more than that of Sn-3.0Ag-0.5Cu in the high-speed shear condition. Moreover, the Sn-Ag-Cu-In joints presented averagely fracture energies similar to those of Sn-Ag-Cu joints. While maximum values in the fracture energies were measured after the solid aging for 100 h, clear decreases in the fracture energies were observed after the solid aging for 500 h. This result indicated that reliability degradation of the Sn-Ag-Cu-In solder joints might accelerate from about that time.