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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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Journal of the Microelectronics and Packaging Society
Journal Basic Information
Journal DOI :
The Korean Microelectronics and Packaging Society
Editor in Chief :
Volume & Issues
Volume 22, Issue 4 - Dec 2015
Volume 22, Issue 3 - Sep 2015
Volume 22, Issue 2 - Jun 2015
Volume 22, Issue 1 - Mar 2015
Selecting the target year
Optimal Interval Censoring Design for Reliability Prediction of Electronic Packages
Kwon, Daeil ; Shin, Insun ;
Journal of the Microelectronics and Packaging Society, volume 22, issue 2, 2015, Pages 1~4
DOI : 10.6117/kmeps.2015.22.2.001
Qualification includes all activities to demonstrate that a product meets and exceeds the reliability goals. Manufacturers need to spend time and resources for the qualification processes under the pressure of reducing time to market, as well as offering a competitive price. Failure to qualify a product could result in economic loss such as warranty and recall claims and the manufacturer could lose the reputation in the market. In order to provide valid and reliable qualification results, manufacturers are required to make extra effort based on the operational and environmental characteristics of the product. This paper discusses optimal interval censoring design for reliability prediction of electronic packages under limited time and resources. This design should provide more accurate assessment of package capability and thus deliver better reliability prediction.
Thermal Management on 3D Stacked IC
Kim, Sungdong ;
Journal of the Microelectronics and Packaging Society, volume 22, issue 2, 2015, Pages 5~9
DOI : 10.6117/kmeps.2015.22.2.005
Thermal management becomes serious in 3D stacked IC because of higher heat flux, increased power generation, extreme hot spot, etc. In this paper, we reviewed the recent developments of thermal management for 3D stacked IC which is a promising candidate to keep Moore's law continue. According to experimental and numerical simulation results, Cu TSV affected heat dissipation in a thin chip due to its high thermal conductivity and could be used as an efficient heat dissipation path. Other parameters like bumps, gap filling material also had effects on heat transfer between stacked ICs. Thermal aware circuit design was briefly discussed as well.
3-D Hetero-Integration Technologies for Multifunctional Convergence Systems
Lee, Kang-Wook ;
Journal of the Microelectronics and Packaging Society, volume 22, issue 2, 2015, Pages 11~19
DOI : 10.6117/kmeps.2015.22.2.011
Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.
Study on the Enhanced Specific Surface Area of Mesoporous Titania by Annealing Time Control: Gas Sensing Property
Hong, M.-H. ; Park, Ch.-S. ; Park, H.-H. ;
Journal of the Microelectronics and Packaging Society, volume 22, issue 2, 2015, Pages 21~26
DOI : 10.6117/kmeps.2015.22.2.021
Mesoporous ceramic materials were applied in various fields such as adsorbent and gas sensor because of low thermal conductivity and high specific surface area properties. This structure could be divided into open-pore structure and closed-pore structure. Although closed-pore structure mesoporous ceramic materials have higher mechanical property than open-pore structure, it has a restriction on the application because the increase of specific surface area is limited. So, in this work, specific surface area of closed-pore structure
was increased by anneal time. As increased annealing time, crystallization and grain growth of
skeleton structured material in mesoporous structure induced a collapse and agglomeration of pores. Through this pore structural change, pore connectivity and specific surface area could be enhanced. After anneal for 24 hrs, porosity was decreased from 36.3% to 34.1%, but specific surface area was increased from
. CO gas sensitivity was also increased by about 7.4 times due to an increase of specific surface area.
Study of Chip-level Liquid Cooling for High-heat-flux Devices
Park, Manseok ; Kim, Sungdong ; Kim, Sarah Eunkyung ;
Journal of the Microelectronics and Packaging Society, volume 22, issue 2, 2015, Pages 27~31
DOI : 10.6117/kmeps.2015.22.2.027
Thermal management becomes a key technology as the power density of high performance and high density devices increases. Conventional heat sink or TIM methods will be limited to resolve thermal problems of next-generation IC devices. Recently, to increase heat flux through high powered IC devices liquid cooling system has been actively studied. In this study a chip-level liquid cooling system with TSV and microchannel was fabricated on Si wafer using DRIE process and analyzed the cooling characteristics. Three different TSV shapes were fabricated and the effect of TSV shapes was analyzed. The shape of liquid flowing through microchannel was observed by fluorescence microscope. The temperature differential of liquid cooling system was measured by IR microscope from RT to
A Study on the Agglomeration of BaTiO
Nanoparticles with Differential Synthesis Route
Han, W.-J. ; Yoo, B.-Y. ; Park, H.-H. ;
Journal of the Microelectronics and Packaging Society, volume 22, issue 2, 2015, Pages 33~39
DOI : 10.6117/kmeps.2015.22.2.033
is typical ferromagnetic materials with dielectric constant of above 200.
nanoparticles applications are available for multiple purposes such as nanocapacitors, ferroelectric random access memories, and so on. Applications are is diverse from the dispersion of nanoparticles depending on the route of synthesis. In this study,
nanoparticles were synthesized by two different methods such as oxalate method and sol-gel process (ambient condition sol method). Particle size and dispersion condition were studied according to the preparation method and capping agent. Poly vinyl pyrrolidone (PVP) was used as a capping agent in oxalate method and tetrabutylammonium hydroxide (TBAH) used as a capping agent in sol-gel process each. Cubic crystal structure of
phase could be confirmed by X-ray diffraction analysis. Fourier transform-infrared spectroscopy was employed for the confirmation of the capping agent and
nanoparticles. The particle size and distribution analysis was also performed by particles size analyzer and scanning electron microscope.
Introduction of Routable Molded Lead Frame and its Application
Kim, ByongJin ; Bang, Wonbae ; Kim, GiJung ; Jung, JiYoung ; Yoon, JuHoon ;
Journal of the Microelectronics and Packaging Society, volume 22, issue 2, 2015, Pages 41~45
DOI : 10.6117/kmeps.2015.22.2.041
RtMLF (Routable Molded Lead Frame) based on molded substrate has been developed to maximize advantages of both leadframe product which has high thermal and electrical performance and laminate product which accommodates more I/O count and keeps fan-in/fan-out design flexibility. Due to its structural features, RtMLF provided excellent thermal and electrical performance which was confirmed with simulation. The RtMLF samples were manufactured and its reliability analysis was done to evaluate the opportunities of the production and application.
Effects of PCB Surface Finishes on in-situ Intermetallics Growth and Electromigration Characteristics of Sn-3.0Ag-0.5Cu Pb-free Solder Joints
Kim, Sung-Hyuk ; Park, Gyu-Tae ; Lee, Byeong-Rok ; Kim, Jae-Myeong ; Yoo, Sehoon ; Park, Young-Bae ;
Journal of the Microelectronics and Packaging Society, volume 22, issue 2, 2015, Pages 47~53
DOI : 10.6117/kmeps.2015.22.2.047
The effects of electroless nickel immersion gold (ENIG) and organic solderability preservative (OSP) surface finishes on the in-situ intermetallics reaction and the electromigration (EM) reliability of Sn-3.0Ag-0.5Cu (SAC305) solder bump were systematically investigated. After as-bonded,
intermetallic compound (IMC) was formed at the interface of the ENIG surface finish at solder top side, while at the OSP surface finish at solder bottom side,
IMCs were formed. Mean time to failure on SAC305 solder bump at
with a current density of
was 78.7 hrs. EM open failure was observed at bottom OSP surface finish by fast consumption of Cu atoms when electrons flow from bottom Cu substrate to solder. In-situ scanning electron microscope analysis showed that IMC growth rate of ENIG surface finish was much lower than that of the OSP surface finish. Therefore, EM reliability of ENIG surface finish was higher than that of OSP surface finish due to its superior barrier stability to IMC reaction.
Novel Low-Volume Solder-on-Pad Process for Fine Pitch Cu Pillar Bump Interconnection
Bae, Hyun-Cheol ; Lee, Haksun ; Eom, Yong-Sung ; Choi, Kwang-Seong ;
Journal of the Microelectronics and Packaging Society, volume 22, issue 2, 2015, Pages 55~59
DOI : 10.6117/kmeps.2015.22.2.055
Novel low-volume solder-on-pad (SoP) process is proposed for a fine pitch Cu pillar bump interconnection. A novel solder bumping material (SBM) has been developed for the
pitch SoP using screen printing process. SBM, which is composed of ternary Sn-3.0Ag-0.5Cu (SAC305) solder powder and a polymer resin, is a paste material to perform a fine-pitch SoP in place of the electroplating process. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder; the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. The Si chip and substrate with daisy-chain pattern are fabricated to develop the fine pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si substrate has 6724 under bump metallization (UBM) with a
pitch. The Si chip with Cu pillar bump is flip chip bonded with the SoP formed substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of underfill. The optimized interconnection process has been validated by the electrical characterization of the daisy-chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and micro bump interconnection using a screen printing process.
Warpage Analysis for Top and Bottom Packages of Package-on-Package Processed with Thin Substrates
Park, D.H. ; Shin, S.J. ; Ahn, S.G. ; Oh, T.S. ;
Journal of the Microelectronics and Packaging Society, volume 22, issue 2, 2015, Pages 61~68
DOI : 10.6117/kmeps.2015.22.2.061
Warpage analysis has been performed for top and bottom packages of thin package-on-packages processed with different epoxy molding compounds (EMCs). Warpage deviation was measured for packages molded with the same EMCs and also the warpage deviations of top and bottom substrates themselves were characterized in order to identify the major factor causing the package warpage. For the top and bottom packages processed with thin substrates, the warpage deviation of the substrates was large, which made it difficult to figure out the effect of EMC properties on the package warpage. Top packages, where the molding area of
covered the most of the substrate area (
), exhibited similar warpage behavior with changing the temperature. On the other hand, bottom packages, where the molding area was only
, exhibited the complex warpage behavior due to simultaneous occurrence of (+) and (-) warpages on the same package. Accordingly, the bottom packages showed dissimilar temperature-warpage behavior even being processed with the same EMCs.