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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
Journal of the Microelectronics and Packaging Society
Journal Basic Information
Journal DOI :
The Korean Microelectronics and Packaging Society
Editor in Chief :
Volume & Issues
Volume 6, Issue 4 - Dec 1999
Volume 6, Issue 3 - Sep 1999
Volume 6, Issue 2 - Jun 1999
Volume 6, Issue 1 - Mar 1999
Selecting the target year
Fabrication process of embedded passive components in MCM-D
Journal of the Microelectronics and Packaging Society, volume 6, issue 4, 1999, Pages 1~7
We developed Fabrication process of embedded passive components in MCM-D substrate. The proposed MCM-D substrate is based on Cu/photosensitive BCB multilayer. The substrate used is Si wafer and Ti/cu metallization is used to form the interconnect layer. Interconnect layers are formed with 1000
Cu by sputtering method and 3
Cu by electrical plating method. In order to form the vias in photosensitive BCB layer, the process of BCB and plasma etch using
gas were evaluated. The MCM-D substrate is composed of 5 dielectric layers and 4 interconnect layers. Embedded resistors are made with NiCr and implemented on the
dielectric layer. The sheet resistance of NiCr is controlled to be about 21
/sq at the thickness of 600
. The multi-turn sprial inductors are designed in coplanar fashion on the
interconnect layer with an underpass from the center to outside using the lower
interconnect layer. Capacitors are designed and realized between
interconnect layer and
interconnect layer. An important issue in capacitor is the accurate determination of the dielectric thickness. We use the 900
thickness of PECVD silicon nitride film as dielectric. Capacitance per unit area is about 88nF/
at the thickness of 900
. The advantage of this integration process is the compatibility with the conventional semiconductor process due to low temperature PECVD silicon nitride process and thermal evaporation NiCr process.
Simultaneous Switching Noise Reduction Technique in Multi-Layer Boards using Conductive Dielectric Substrate
Journal of the Microelectronics and Packaging Society, volume 6, issue 4, 1999, Pages 9~14
In this paper, we proposed a simultaneous switching noise (SSN) reduction technique in multi-layer boards (MLB) for high-speed digital applications and analyzed it using the Finite Difference Time Domain (FDTD) method. The new structure using conductive dielectric substrates is effective for the reduction of SSN couplings and resonances. The uniform insertion of the conducive layer reduced the SSN coupling and resonance by 85% and the partial insertion only around the edges reduced by 55% respectively.
Development of Build up Multilayer Board Rapid Manufacturing Process Using Screen Printing Technology
Journal of the Microelectronics and Packaging Society, volume 6, issue 4, 1999, Pages 15~22
Generally, many equipments and a long lead time ale required to manufacture the build-up multilayer board through various processes such as etching, plating, drilling etc. Wet process is suitable for mass production, however it is not adequate for manufacturing prototype in developing stage. In this study, a silk screen printing technology is introduced to make a prototype build-up multilayer board. As for the material photo/thermal curable resin and conductive paste are used for forming dielectric and conductor. And conductive paste fills vias for interconnecting each layer, and also is used for circuit patterning by silk screen technology. Finally, the basic concept and the possibility of build-up multilayer board prototype is proposed and verified as a powerful approach, compared with the conventional processes.
Thermal and Stress Analysis of Power IGBT Module Package by Finite Element Method
Journal of the Microelectronics and Packaging Society, volume 6, issue 4, 1999, Pages 23~33
A finite element method was employed fort thermal and stress analyses of an IGBT module of 3-phase full bridge. The effect of material parameters such as substrate material, substrate area, solder thickness on the temperature and stress distributions of the module packages has been investigated. Thermal analysis results have also been compared by setting of boundary conditions such as equivalent heat transfer coefficient or constant temperature at a base metal surface of the package. The increase of ceramic substrate area up to 3 times does little contribution to the reduction(8.9%) of thermal resistance, while contributed a lot to the reduction(60%) of thermal stress. Thicker solder resulted in higher thermal resistance but did slightly reduced thermal stresses. It is revealed by the stress analysis that maximum stress was induced at the region of copper pads which are bonded with ceramic substrate.
The Fabrication of Low Temperature Firing Substrate of
Park, Jung-Houn ; Park, Dae-Hyun ; Kang, Won-Ho ;
Journal of the Microelectronics and Packaging Society, volume 6, issue 4, 1999, Pages 35~39
glasses with addition of
were investigated in order to make glass-ceramics for low temperature firing substrate. Glasses were made by melting at
in the electronic furnace and crystallized at
. The crystal phases were polycrystalline of lithium boron fluorphlogopite and lithium fluorhectorite. The crystal shape was chanced to granule type from needle type with increasing
content. Average particle size of the glass-ceramics after water swelling was
. The optimum sintering temperature and sintering shrinkage of the substrate were
and 13.4%, respectively.
The study on the properties of binary mixture(crystalline silica/AIN) filled EMC(Epoxy Molding Compounds)
Journal of the Microelectronics and Packaging Society, volume 6, issue 4, 1999, Pages 41~48
Silica is the most popular materials as a filler of EMC for microelectronic packaging. However, because of its low thermal conductivity, the use of silica is restricted to parts requiring high thermal dissipation. The superior fluidity of EMC can be achieved with a combination of filler size distribution. In this study, physical properties of EMC filled with the crystalline silica(13
) which have high fluidity and low cost and the AlN(2
) which have high thermal conductivity and low coefficient of thermal expansion were evaluated by changing the AlN/silica ratios. As a result of the evaluation of physical properties of EMC, the optimum mixing ratio of AlN/crystalline silica was 0.3/0.7. In this condition, binary mixture(AlN/crystalline silica) filled EMC showed superior properties, i.e., in the thermal conductivity, CTE, dielectric constant, flexural strength, and thermal shock resistance without reduction of fluidity.
Study on the structure of buried type capacitor for MCM (Multi-Chip-Module)
Journal of the Microelectronics and Packaging Society, volume 6, issue 4, 1999, Pages 49~53
In this study, the characteristics of the structure of buried type capacitor for RF multi- chip-module are investigated. We developed many kinds of structures to minimize the space of capacitor in module and the value of parastic series inductance without any loss in capacitance, and in this procedure the effect of vias especially position, size, number length are analyzed and optimized. This characteristics of structures are checked through HFSS(high frequency structure simulator) of HP, and the value of parastic series inductance is calculated by equivalent circuit analysis. And ensuing the result of simulation, we made buried type capacitors using LTCC (low temperature cofired ceramic) material. In measurement of this sample, we found out the effective and precise method can be applied to buried type and characteristics of vias and striplines added for measuring are quantified.
Fabrication of Bi based solder glass
Journal of the Microelectronics and Packaging Society, volume 6, issue 4, 1999, Pages 55~59
One of lead free glass, Bi based solder glass is investigated for electronic packaging application. The melting temperature of glass about
at Bi based glass (70wt%
+lwt% ZnO) and varied with
content in this system. Crystallized glasses were obtainded after 1hr heat teratment at
with 10wt% of
addition. Much higher melting temperature was observed at
rich composition area.
Overview on Flip Chip Technology for RF Application
Journal of the Microelectronics and Packaging Society, volume 6, issue 4, 1999, Pages 61~71
The recent trend toward higher frequencies, miniaturization and lower-cost in wireless communication equipment is demanding high density packaging technologies such flip chip interconnection and multichip module(MCM) as a substitute of conventional plastic package. With analyzing the recently reported research results of the RF flip chip, this paper presents the technical issues and advantages of RF flip chip and suggest the flip chip technologies suitable for the development stage. At first, most of RF flip chips are designed in a coplanar waveguide line instead of microstrip in order to achieve better electrical performance and to avoid the interaction with a substrate. Secondly, eliminating wafer back-side grinding, via formation, and back-side metallization enables the manufacturing cost to be reduced. Finally, the electrical performance of flip chip bonding is much better than that of plastic package and the flip chip interconnection is more suitable for Transmit/Receiver modules at higher frequency. However, the characterization of CPW designed RF flip chip must be thoroughly studied and the Au stud bump bonding shall be suggested at the earlier stage of RF flip chip development.
Environmental Changes & Technical Responses in Printed Circuit Board Industry
Journal of the Microelectronics and Packaging Society, volume 6, issue 4, 1999, Pages 73~77
Revolutionary changes on multimedia, network and PDA(Personal digital assistants) causes PCB(Printed circuit beard) manufacturers to change their attitudes to product. Traditional idea for current market such as price, market, and service has collapsed down and new digitalization urges PCB manufacturers to deal with new technologies, shorter lead time with reasonable price, high qualities. Therefore PCB manufacturers have an effort to develop new marketing, products, processes for low cost to keep up pace with assembly makers.