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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
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Journal of the Microelectronics and Packaging Society
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Journal DOI :
The Korean Microelectronics and Packaging Society
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Volume & Issues
Volume 8, Issue 4 - Dec 2001
Volume 8, Issue 3 - Sep 2001
Volume 8, Issue 2 - Jun 2001
Volume 8, Issue 1 - Mar 2001
Selecting the target year
On the Development of an Inspection Algorithm for Micro Ball Grid Array Solder Balls
Journal of the Microelectronics and Packaging Society, volume 8, issue 3, 2001, Pages 1~9
This paper proposes an inspection algorithm for micro ball grid array (
BGA) solder balls. This algorithm is motivated by the difficulty of finding defect balls by human visual inspection due to their small dimensions. Specifically, it is developed herein an automated vision-based inspection algorithm for
BGA's, which can inspect solder balls not only for so-called two dimensional errors, such as missings, positions and sizes, but also for height errors. The inspection algorithm uses two dimensional images of
BGA obtained through special blue illumination, and processes them with a rotation-invariant sub algorithm. It can also detect height errors when a two-camera system is available. Simulation results show that the proposed algorithm is more efficient in detecting ball defects compared with the conventional algorithms.
A Knowledge-based Design System for Injection Molding
Huh, Yong-Jeong ;
Journal of the Microelectronics and Packaging Society, volume 8, issue 3, 2001, Pages 11~17
The design and manufacture of injection molded polymeric parts with desired properties is a costly process dominated by empiricism, including the repeated modification of actual tooling. This paper presents an expert design evaluation system which can predict the mechanical performance of a molded product and diagnose the design before the actual mold is machined. The knowledge-based system synergistically combines a rule-based expert system with CAE programs. Heuristic knowledge of injection molding is formalized as rules of an expert consultation system. The expert system interprets the analytical results of the process simulation, predicts the performance, evaluates the design and generates recommendations for optimal design alternatives.
The Application of Electropolishing for Removing Burrs and Residual Stress of Stamping Leadframe
Journal of the Microelectronics and Packaging Society, volume 8, issue 3, 2001, Pages 19~24
The lead frame, which is principal material used in semiconductor packaging, is required to be microscopic in leads and pitches to cope with miniaturization, thin film, large scale integrated. In addition, it is indispensable to eliminate residual stress and burrs occurring at manufacturing lead frames This thesis applied electrolytic abrasion in order to remove burrs and residual stress created during the stamp process. Electrolytic abrasion removed the burrs on the surface of lead frame. Removal of residual stress highly depends on the types of electrolyte solution. In case of perchloric system, electrolytic abrasion removed 23% of residual stress. Through removal of burrs and reducing residual stress, the reliability of lead frame was substantially improved.
Boundary Element Analysis for Edge Cracks at the Bonding Interface of Semiconductor Chip
Journal of the Microelectronics and Packaging Society, volume 8, issue 3, 2001, Pages 25~30
The stress intensity factors for edge cracks located at the bonding interface between the semiconductor chip and the adhesive layer subjected to a uniform transverse tensile strain are investigated. Such cracks might be generated due to a stress singularity in the vicinity of the free surface. The boundary element method (BEM) is employed to investigate the behavior of interface stresses. The amplitude of complex stress intensity factor depends on the crack length, but it has a constant value at large crack lengths. The rapid propagation of interface crack is expected if the transverse tensile strain reaches a critical value.
A Study on Development of Dielectric Layers for High-Temperature Electrostatic Chucks
Journal of the Microelectronics and Packaging Society, volume 8, issue 3, 2001, Pages 31~36
Dielectric material which is suitably designed for the application of the high-temperature electrostatic chucks(HTESCS) has been developed. Electrical resistivities and dielectric constants of the dielectric layer satisfy the demands for the proper operation of HTESC, and coefficient of thermal expansion(CTE) of the dielectric material matches well that of the bottom insulator so that it secures stable structure. In order to minimize particle contaminations, borosilicate glass(BSG) is selected as a bonding layer between dielectric layer and bottom insulator, and silver is used as a electrode. BSG is solidly bonded between upper dielectric and bottom insulator, and no diffusions or reactions are observed among silver electrode, dielectric, and glass layers. The chucking characteristics of the fabricated HTESC are found to be superior to those of the commercialized one.
Characteristic of Intermetallic Compounds for Aging of Lead Free Solders Applied to 48
Journal of the Microelectronics and Packaging Society, volume 8, issue 3, 2001, Pages 37~42
The concerns of the toxicity and health hazard of lead in solders have demanded the research to find suitable lead-free solder alloys. It was discussed that effect of the intermetallic formation and structure on the reliability of solder joints. In this study, lead-free solder alloys with compositions of Sn/3.5Ag/0.75Cu, Sn/2.0Ag/0.5Cu/2.0Bi were applied to the 48
BGA packages. Also, the lead-free solder alloys compared with eutectic Sn/37Pb solder using shear test under various aging temperature. Common
BGA with solder components was aged at
. And the each temperature applied to 300, 600 and 900 hours. The thickness of the intermetallics was measured for each condition and the activation energy for their growth was computed. The fracture surfaces were analyzed using SEM (Scanning Electron Microscope) with EDS (Energy Dispersive Spectroscopy). These results for reliability of lead-free interconnections are discussed.
A Study on the Solderability of In and Bi Contained Sn-Ag Alloy
Journal of the Microelectronics and Packaging Society, volume 8, issue 3, 2001, Pages 43~47
Sn-3Ag-8Bi-5In was developed for the intermediate melting point solder. Although In-contained solder is expensive, its melting point is lower than these of Sn-Ag-Cu alloys. Sn-3Ag-8Bi-5In solder used for this research has a melting range of 188~
. On this study wetting characteristics of Sn-3Ag-8Bi-5In were evaluated in order to investigate its availability as a Pb-free solder. Wettabilities of Sn-37Pb and Sn-3.5Ag solders were also studied to compare these of the Sn-3Ag-8Bi-5In. Experimental results showed that the zero-cross-time and wetting time at
for the Sn-3Ag-8Bi-5In were 1.1 and 2.2 second respectively. These values are a little better than these of Sn-37Pb and Sn-3.5Ag solders. The equilibrium wetting farce of the Sn-3Ag-8Bi-5In was 5.8 mN at
, and it was tuned out to be a little higher than that of Sn-3.5Ag and lower than that of Sn-37Pb.
Vortical Etching Characteristics of SrBi
thin Films Depending on Ar/Cl
Ratios and RF/DC Power Densities
Journal of the Microelectronics and Packaging Society, volume 8, issue 3, 2001, Pages 49~53
Vortical etching experiments of (
)/Si thin films have been performed by using the inductively coupled plasma reactive ion etching (ICP-ME) apparatus. The purposes of these experiments are to get the effective area of vertical surface. Because this technology is very important to get good qualities of ferroelectric gate structure, capacitor and the minimum parasitic effects related to the excellent performances of the FRAM (Ferroelectric Random Access Memory) device. The reacting gases were Ar and
gases, and various
flow ratios were used. The etching experiments were carried out at various RF powers such as 700, 700, 500W and at various DC powers such as 200, 150, 100, 50W, respectively. The maximum etch rate of
/Si thin films was 1050 A/min at the
gas ratio of 20/16, RF power of 700 W and DC power of 200 W. From the SEM (scanning electron microscopy) image of the SBT thin films, the wall angle was as good as about
Study on the Improvement of BGA Solderability in Electroless Nickel/Gold Deposit
Journal of the Microelectronics and Packaging Society, volume 8, issue 3, 2001, Pages 55~62
With a spread of BGA, CSP and fine pitch devices, the need of flatter surface finish in bare board is becoming more critical in solderability. The electroless Ni/Au plating has a solution of these needs and also has being spread to apply to surface finish for bare board in many electronic goods. But, the electroless Ni/Au plating had several issues such as Ni oxidation and phosphorous contents. Before this study, we studied on the effect of BGA solderability in electroless Ni/Au plating and chose some major factors such as the oxidation property of NiP plating and warpage of board. Firstly, we made test board with various plating conditions and improved the plating property through the improvement of NiP oxidation reducing P content. Also, we minimized the warpage of board with the improvement of inner layer structure and the analysis of warpage. For the evaluation of solderability, we analyzed the warpage of board and the plating property after mounting BGA on the board with optimizing conditions. The solder joint of BGA is investigated by SEM(Scanning Electronic Microscope) and OM(Optical Microscope). The composition of joint is used by EDS(Energy Dispersive Spectroscopy). We analyzed the fracture strength and mode by ball shear teser.
Study on the Surface Reaction of Pt Thin Film with SF
/Ar and Cl
/Ar Plasma Gases
Journal of the Microelectronics and Packaging Society, volume 8, issue 3, 2001, Pages 63~67
Up to now, most studies about Pt-etching have been focused on physical sputtering mechanism with Cl-based plasma, while only a limited results are available for etching characteristics with fluorine-based plasma. In this study, etch characteristics of Pt thin film with
/Ar Ar gas chemistries have been studied with ECR plasma etching system. It is confirmed that
/Ar Ar plasma chemistry could make volatile etch-products through the reaction with Pt thin film. Also the improvement in etch rate, etch profile and surface roughness is obtained due to the formation of volatile platinum fluoride compounds.
Formation of Fine Line and Series Gap Resonator Using the Photoimageable Thick Film Technology
Journal of the Microelectronics and Packaging Society, volume 8, issue 3, 2001, Pages 69~75
Photoimageable thick film technology is a new technology in that the lithography process such as exposure and development is applied to the conventional thick film process. Line resolution of 25
width and 25
space could be obtained by laminating green sheet, printing photoimageable Ag paste, exposing the test patterns, developing, and co-firing. In case of using the alumina substrate, 20
fine line could be also obtained by similar process. Test results showed that exposing power density and developing time were the most important processing parameters for the fine line formation. Microstrip and series gap resonators with well-defined line morphology and good transmission characteristics in high frequency were formed by this new technology, and thereby dielectric constant and loss of test substrate were calculated.