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REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
Journal of the Microelectronics and Packaging Society
Journal Basic Information
Journal DOI :
The Korean Microelectronics and Packaging Society
Editor in Chief :
Volume & Issues
Volume 9, Issue 4 - Dec 2002
Volume 9, Issue 3 - Sep 2002
Volume 9, Issue 2 - Jun 2002
Volume 9, Issue 1 - Mar 2002
Selecting the target year
Reaction Characteristics between In-l5Pb-5Ag Solder and Au/Ni Surface Finish and Reliability Evaluation of Solder Joint
Journal of the Microelectronics and Packaging Society, volume 9, issue 4, 2002, Pages 1~9
The metallurgical reaction properties between the pad consisted of 0.5
Ni/Cu layers on a conventional ball grid array (BGA) substrate and In-15 (wt.%)Pb-5Ag solder ball were characterized during the reflow process and solid aging. During the reflow process of 1 to 5 minutes, it was observed that thin
or Ni-In intermetallic layer was formed at the interface of solder/pad. The dissolution rate of the Au layer into the molten solder was about
/sec which is remarkably low in comparison with a eutectic Sn-37Pb solder. After solid aging treatment for 500 hrs at
, the thickness of
intermetallic layer was increased to about 3
in all the conditions nevertheless the initial reflow time was different. These result show that In atoms in the solder alloy were diffused through the
phase to react with underlaying Ni layer during solid aging treatment. From the microstructural observation and shear tests, the reaction properties between In-15Pb-5Ag alloy and Au/Ni surface finish were analyzed not to trigger Au-embrittlement in the solder joints unlike Sn-37Pb composition.
Physical and Electrical Characteristics of SrBi
thin Films Etched with Inductively Coupled Plasma Reactive Ion Etching System
Journal of the Microelectronics and Packaging Society, volume 9, issue 4, 2002, Pages 11~16
In this study, the dry etching characteristics of
(SBT) thin films were investigated by using ICP-RIE (inductively coupled plasma-reactive ion etching). The etching damage and degradation were analyzed with XPS (X-ray photoelectron spectroscopy) and C-V (Capacitance-Voltage) measurement. The etching rate increased with increasing the ICP power and the capacitively coupled plasma (CCP) power. The etch rate of 900
/min was obtained with 700 W of ICP power and 200 W of CCP power. The main problem of dry etching is the degradation of the ferroelectric material. The damage-free etching characteristics were obtained with the
gas mixture of 20/14/2 when the ICP power and CCP power were biased at 700 W and 200 W, respectively. The experimental results show that the dry etching process with ICP-RIE is applicable to the fabrication of the single transistor type ferroelectric memory device.
Effects of Trench Depth on the STI-CMP Process Defects
Journal of the Microelectronics and Packaging Society, volume 9, issue 4, 2002, Pages 17~23
The more productive and stable fabrication can be obtained by applying chemical mechanical polishing (CMP) process to shallow trench isolation (STI) structure in 0.18
semiconductor device. However, STI-CMP process became more complex, and some kinds of defect such as nitride residue, tern oxide defect were seriously increased. Defects like nitride residue and silicon damage after STI-CMP process were discussed to accomplish its optimum process condition. In this paper, we studied how to reduce torn oxide defects and nitride residue after STI-CMP process. To understand its optimum process condition, We studied overall STI-related processes including trench depth, STI-fill thickness and post-CMP thickness. As an experimental result showed that as the STI-fill thickness becomes thinner, and trench depth gets deeper, more tern oxide were found in the CMP process. Also, we could conclude that low trench depth whereas high CMP thickness can cause nitride residue, and high trench depth and over-polishing can cause silicon damage.
Characteristic Analysis of The Vertical Trench Hall Sensor using SOI Structure
Journal of the Microelectronics and Packaging Society, volume 9, issue 4, 2002, Pages 25~29
We have fabricated a vertical trench Hall device which is sensitive to the magnetic field parallel to the sensor surface. The vertical trench Hall device has been built on SOI wafer which is produced by silicon direct bonding technology using bulk micromachining, where buried
layer and surround trench define active device volume. Sensitivity up to 150 V/AT has been measured.
Investigation of Adhesion Mechanism at the Metal-Organic Interface Modified by Plasma Part I
Sun, Yong-Bin ;
Journal of the Microelectronics and Packaging Society, volume 9, issue 4, 2002, Pages 31~34
For the mold die sticking mechanism, the major explanation is that the silica as a filler in EMC (epoxy molding compound) wears die surface to be roughened, which results in increase of adhesion strength. As the sticking behavior, however, showed strong dependency on the EMC models based on the experimental results from different semiconductor manufacturers, chemisorption or acid-base interaction is apt to be also functioning as major mechanisms. In this investigation, the plasma source ion implantation (PSII) using
modifies sample surface to form a new dense layer and improve surface hardness, and change metal surface condition from hydrophilic to hydrophobic or vice versa. Through surface energy quantification by measuring contact angle and surface ion coupling state analysis by Auger, major governing mechanism for sticking issue was figured out to be a complex of mechanical and chemical factors.
Analysis of Stresses Along the Underfill/chip Interface
Park, Ji-Eun ; Iwona Jasiuk ; Lee, Ho-Young ;
Journal of the Microelectronics and Packaging Society, volume 9, issue 4, 2002, Pages 35~45
The stresses of the underfill/chip interface due to thermal loading was studied using the finite element method. At first, the effective properties of underfill for several volume fractions of silica particles were calculated by Mori-Tanaka method for three different material sets, and the parameters of singularity for the bimaterial edge and the bimaterial wedge were calculated. Consequently, the stresses at the underfill/chip interface with volume fraction of silica particles were investigated. Five different geometric models of flip-chip assembly involving two kinds of bimaterial strips and three kinds of three-layer models were considered under the assumption that the underfill is homogeneous. It was assumed that all components of the flip-chip assembly were linear elastic and isotropic, and their properties were temperature independent. The analysis was conducted in the context of the uncoupled plane thermo-elasticity under a plane strain assumption.
Enhancement of Lowsintering Temperature and Electromagnetic Properties of (NiCuZn)-Ferrites for Multilayer Chip Inductor by Using Ultra-fine Powders
Journal of the Microelectronics and Packaging Society, volume 9, issue 4, 2002, Pages 47~53
In this study, two different (NiCuZn)-ferrite which were fabricated by using ultra-fine powders synthesized by the wet processing and conventionally commercialized powder, were investigated and compared each other in terms of the low temperature sintering and electromagnetic properties. Composition of x and w in
were controlled as 0.2 and 0.03, respectively. The sintering temperature were
for ultra-fine powders by way of initial heat treatment and
for commercialized powders. The (NiCuZn)-ferrite by ultra-fine powders showed love. sintering temperature than that of commercialized powders by over
, and excellent electromagnetic properties such as the quality factor which is a important factor in the multi-layered chip inductor. In addition, characteristics of B-H hysteresis, crystallinity, microstructure and powder morphology were analyzed by a vibrating sample method(VSM), x-ray diffractometer(XRD), transmission electron microscope (TEM) and scanning electron microscope(SEM).
The Vertical Alignment of CNTs and Ni-tip Removal by Etching at ICPHFCVD
Journal of the Microelectronics and Packaging Society, volume 9, issue 4, 2002, Pages 55~60
This paper presents a technique for the preparation of vertically grown CNTs by ICPHFCVD(inductively coupled plasma hot filament chemical vapor deposition) below
. Purification of the CNTs(carbon nanotubes) using RE(radio frequency) plasma in a one step process, based on the different etching property of the Ni-tip, amorphous carbon and carbonaceous materials is also discussed. After purifying the grown materials. CNTs shown the multi walled and hollow typed structure. The typical outer and inner diameters or CNT were 50 nm and 25 nm, respectively. The graphitic wall was composed of 82 layers and the distance between wall and wall was 0.34 nm. From the results of TEM observation, the Ni catalyst at the tip of the carbon nanotubes were effectively removed by using a RF plasma etching, continuously.
Evaluation of Mechanical Stress for Solder Joints
Journal of the Microelectronics and Packaging Society, volume 9, issue 4, 2002, Pages 61~68
Thermal shock testing was used to evaluate reliability that appeared in the solder joints of electronic devices when they were subjected to thermal cycling. Recently, mobile devices have come smaller and multi-functional, with the increasing need for high-density packaging, BGA or CSP has become the main trend for surface mounting technology, and therefore mechanical stress life for solder joints in BGA/CSP type packages has required. Reliability of BGA/CSP solder joints was evaluated with electric resistivity change of daisy chain pattern and stress-strain curve measured using strain gage attached on the surface of PCB under mechanical impact loading. In this report, applications of PCB Universal Testing Machine we have developed and experimental datum of SONY estimating dynamic behavior of mechanical stress in BGA/CSP solder joints are introduced.