Go to the main menu
Skip to content
Go to bottom
REFERENCE LINKING PLATFORM OF KOREA S&T JOURNALS
> Journal Vol & Issue
Journal of the Korea Industrial Information Systems Research
Journal Basic Information
Journal DOI :
The Korea Society for Industrial Systems
Editor in Chief :
Volume & Issues
Volume 18, Issue 6 - Dec 2013
Volume 18, Issue 5 - Oct 2013
Volume 18, Issue 4 - Aug 2013
Volume 18, Issue 3 - Jun 2013
Volume 18, Issue 2 - Apr 2013
Volume 18, Issue 1 - Feb 2013
Selecting the target year
Design of Variable Gain Amplifier without Passive Devices
Cho, Jong Min ; Lim, Shin Il ;
Journal of the Korea Industrial Information Systems Research, volume 18, issue 5, 2013, Pages 1~8
DOI : 10.9723/jksiis.2013.18.5.001
This paper presents a variable gain amplifier(VGA) without passive devices. This VGA employes the architecture of current feedback amplifier and variable gain can be achieved by using the GM ratios of two trans-conductance(gm) circuits. To obtain linearity and high gain, it uses current division technique and source degeneration in feedback GM circuits. Input trans-conductance(GM) circuit was biased by using a tunable voltage controller to obtain variable gain. The prototype of the VGA is designed in
CMOS technology and it is operating in sub-threshold region for low power consumption. The the gain of proposed VGA is varied from 23dB to 43dB, and current consumption is
at 3.3V. The area of VGA is 1
A Low-power, Low-noise DLL-based Frequency Multiplier for Reference Clock Generator
Kim, Hyung Pil ; Hwang, In Chul ;
Journal of the Korea Industrial Information Systems Research, volume 18, issue 5, 2013, Pages 9~14
DOI : 10.9723/jksiis.2013.18.5.009
This paper is designed frequency multiplier with low phase noise using DLL technique. The VCDL is designed using a differential structure to reduce common-mode noise. The proposed frequency multiplier is fabricated in a 65nm, 1.2V TSMC CMOS process, and the operating frequency range from 10MHz to 24MHz was measured. The SSB phase noise is measured to be -125dBc/Hz at 1MHz from 38.4MHz carrier. A total area of
were consumed in the chip, including the output buffer. Total current is 1.8mA at 1.2V supply voltage.
Implementation of an analog front-end for electroencephalogram signal processing
Kim, Min-Chul ; Shim, Jae Hoon ;
Journal of the Korea Industrial Information Systems Research, volume 18, issue 5, 2013, Pages 15~18
DOI : 10.9723/jksiis.2013.18.5.015
This paper presents an analog front-end for electroencephalogram(EEG) signal processing. Since EEG signals are typically weak and located at very low frequencies, it is imperative to implement an amplifier with high gain, high common-mode rejection ratio(CMRR) and good noise immunity at very low frequencies. The analog front-end of this paper consists of a programmable-gain instrumentation amplifier and a band-pass filter. A frequency chopping technique is employed to remove the low-frequency noise. The circuits were fabricated in 0.18um CMOS technology and measurements showed that the analog front-end has the maximum gain of 60dB and >100dB CMRR over the programmable gain range.
High Speed TCAM Design using SRAM Cell Stability
Ahn, Eun Hye ; Choi, Jun Rim ;
Journal of the Korea Industrial Information Systems Research, volume 18, issue 5, 2013, Pages 19~23
DOI : 10.9723/jksiis.2013.18.5.019
This paper deals with the analysis of 6T SRAM cell stability for Hi-speed processing Ternary Content Addressable Memory. The higher the operation frequency, the smaller CMOS technology required in the designed TCAM because the purpose of TCAM is high-speed data processing. Decrease of Supply voltage is one cause of unstable TCAM operation. Thus, We should design TCAM through analysis of SRAM cell stability. In this paper we propose methodology to characterize the Static Noise Margin of 6T SRAM. All simulations of the TCAM have been carried out in 180nm CMOS process technology.
A 2-Gb/s SLVS Transmitter for MIPI D-PHY
Baek, Seung Wuk ; Jeong, Dong Gil ; Park, Sang Min ; Hwang, Yu Jeong ; Jang, Young Chan ;
Journal of the Korea Industrial Information Systems Research, volume 18, issue 5, 2013, Pages 25~32
DOI : 10.9723/jksiis.2013.18.5.025
A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a 0.18-
1-poly 6-metal CMOS with a 1.8 V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gb/s. The area and power consumption of the 1-lane of the proposed SLVS TX are
and 5.35 mW/Gb/s, respectively.
Design of an SDRAM Controller for AMBA AHB-Lite
Kim, Sang Don ; Lee, Seung Eun ;
Journal of the Korea Industrial Information Systems Research, volume 18, issue 5, 2013, Pages 33~37
DOI : 10.9723/jksiis.2013.18.5.033
In this paper, we introduce a SDRAM controller implemented on FPGA. Modern embedded system adopts SDRAM as a memory to meet the high capacity memory demands. Our SDRAM controller is written in Verilog and verified on an FPGA, demonstrating the functionality along with ARM Cortex-M0, supporting AMBA AHB.
A Design of 18 MHz Relaxation Oscillator with ±1 % Accuracy Based on Temperature Sensor
Kim, Sang Yun ; Lee, Ju Ri ; Lee, Dong Soo ; Park, Hyung Gu ; Kim, Hong Jin ; Lee, Kang-Yoon ;
Journal of the Korea Industrial Information Systems Research, volume 18, issue 5, 2013, Pages 39~44
DOI : 10.9723/jksiis.2013.18.5.039
In this paper, a Relaxation Oscillator with temperature compensation using BGR and ADC is presented. The current to determine the frequency of Relaxation Oscillator can be controlled. By adjusting the current according to the temperature using the code that is output from the ADC and BGR, was to compensate the output frequency of the temperature. It is fabricated in a 0.35
CMOS process with an active area of
. Current consumption is 600
from a 5 V and the rate of change of the output frequency with temperature shows about
Development of FPGA-based failure detection equipment for SMART TV embedded camera
Lee, Jun Seo ; Kim, Whan Woo ; Kim, Ji-Hoon ;
Journal of the Korea Industrial Information Systems Research, volume 18, issue 5, 2013, Pages 45~50
DOI : 10.9723/jksiis.2013.18.5.045
Recently, as the market for SMART TV expands, the camera is embedded for providing various user experience. However, this leads to occurrence of camera failure due to TV power up sequence problem, which are usually not detectable in conventional test equipments. Although the failure-detection can be possible by re-generating control signals for audio interface with new equipment, it is expensive and also requires much time to test. In this paper, for SMART TV, FPGA(Field Programmable Gate Array)-based failure-detection system is proposed which can lead to reduction of both cost and time for test.
Design of clock duty-cycle correction circuits for high-speed SoCs
Han, Sang Woo ; Kim, Jong Sun ;
Journal of the Korea Industrial Information Systems Research, volume 18, issue 5, 2013, Pages 51~58
DOI : 10.9723/jksiis.2013.18.5.051
A clock duty-cycle corrector (DCC) which is an essential device of clocking circuits for high-speed system-on-chip (SoC) design is introduced in this paper. The architectures and operation of conventional analog feedback DCCs and digital feedback DCCs are compared and analyzed. A new mixed-mode feedback DCC that combines the advantages of analog DCCs and digital DCCs to achieve a wider duty-cycle correction range, higher operating frequency, and higher duty-cycle correction accuracy is presented. Especially, the architectures and design of a mixed-mode duty-cycle amplifier (DCA) which is a core unit circuit of a mixed-mode DCC is presented in detail. Two mixed-mode DCCs based on a single-stage DCA and a two-stage DCA were designed in a 0.18-
CMOS process, and it is proven that the two-stage DCA-based DCC has a wider duty-cycler correction range and smaller duty-cycle correction error.
Design and Implementation of Low power ALU based on NCL (Null Convention Logic)
Kim, Kyung Ki ;
Journal of the Korea Industrial Information Systems Research, volume 18, issue 5, 2013, Pages 59~65
DOI : 10.9723/jksiis.2013.18.5.059
Conventional synchronous design circuits cannot only satisfy the timing requirement of the low voltage digital systems, but also they may generate wrong outputs under the influence of PVT variations and aging effects. Therefore, in this paper, a NCL (Null Convention Logic) design as an asynchronous design method has been proposed, where the NCL method doesn't require any timing analysis, and it has a very simple design methodology. Base on the NCL method, a new low power reliable ALU has been designed and implemented using MagnaChip-SKhynix 0.18um CMOS technology. The experimental results of the proposed NCL ALU have been compared to those of a conventional pipelined ALU in terms of power consumption and speed.
A Design of Low-Power Bypassing Booth Multiplier
Ahn, Jong Hun ; Choi, Seong Rim ; Nam, Byeong Gyu ;
Journal of the Korea Industrial Information Systems Research, volume 18, issue 5, 2013, Pages 67~72
DOI : 10.9723/jksiis.2013.18.5.067
A low-power bypassing Booth multiplier for mobile multimedia applications is proposed. The bypassing structure directly transfers input values to outputs without switching the internal nodes of a multiplier, enabling low-power design. The proposed Booth multiplier adopts the bypassing structure while the bypassing is usually adopted in the Braun multipliers. Simulation results show the proposed Booth multiplier achieves an 11% reduction in terms of the proposed FoM compared to prior works.
Voltage Balancing Circuit for Li-ion Battery System
Park, Kyung Hwa ; Yi, Kang Hyun ;
Journal of the Korea Industrial Information Systems Research, volume 18, issue 5, 2013, Pages 73~80
DOI : 10.9723/jksiis.2013.18.5.073
Recently, Li-ion battery is regarded as a potential energy storage device in the lime light and it can supply power to the satellite very effectively during eclipse. Because it has better features as high voltage range, large capacity and small volume than any other battery. Generally, multi cells are connected in series to use Li-ion batteries in satellite application. Since the internal resistance of cells is different each other, voltage in some cells can be overcharged or undercharged, so capacity of the cell is reduced and the life of whole battery pack is decreased. Therefore, a voltage balancing circuit with Fly-back converter is proposed and the voltage equalization of each cell is verified the prototype in this paper.
A Design of Fire-Command Synchronous Satellite Pyrotechnic Circuit
Koo, Ja Chun ; Ra, Sung Woong ;
Journal of the Korea Industrial Information Systems Research, volume 18, issue 5, 2013, Pages 81~92
DOI : 10.9723/jksiis.2013.18.5.081
The satellite includes many release mechanisms such as solar array deployment, antenna deployment, cover to protect contamination in scientific equipment, pyro value of the propulsion subsytem, and bypass device in Li-Ion cell module. A drive the initiators is a critical to the successful mission because the initiators of release mechanism driving by the pyrotechnic circuit is operated in single short. The pyrotechnic circuit has to provide switching network for safety. A typical switching network has defect consisting of high current rating fire switch to handle switching transient current during fire the initiator. The pyrotechnic circuit is required some form of power conditioning to reduce the peak power demanded from the bus if the initiators are to be fired from the main bus. This paper design a pyrotechnic circuit synchronized to the fire-command to activate the fire switch to overcome use high current rating fire switch to handle switching transient current during fire the initiator. The pyrotechnic circuit provides a current limited widow pulse for fire current synchronized to the fire-command to insure that fire switch will only carry the current but never switch it. The current limited widow pulse for fire current can be possible to use low current rating and light mass switch in switching network. The current limit function in the pyrotechnic circuit reduces supply voltage to initiator and provides the effect of power conditioning function to reduce peak bus power. The pyrotechnic circuit to apply satellite development on geostationary orbit is verified the function by test in development model.
A Study on Effective Website Implementation through Comaprison Analysis of the Shopping Mall Websites in Korea and China
Kwon, Young Jik ;
Journal of the Korea Industrial Information Systems Research, volume 18, issue 5, 2013, Pages 93~105
DOI : 10.9723/jksiis.2013.18.5.093
This paper mainly focuses on comparison analysis of the quality factors targeted at one shopping mall web site in Korea and China. There are a total of 14 hypothesis, and we use the SAS 9.2 statistical package tool. The survey to verify those hypothesis is filled out by 519 voluntary participants. The following describes the results that are found. The shopping mall web site of two countries shows a difference in terms of design, communication, community, commercialization, security, customer satisfaction, repurchase intention, contents, e-commerce, customer loyalty, interaction, technology, reliability, and size. Therefore, we suggest how to implement more effective shopping mall websites based on those 14 factors.
A Study on the Moderating Effects of the R&D Fund Management System between National R&D Fund and Research Performance
Son, Chung Geun ;
Journal of the Korea Industrial Information Systems Research, volume 18, issue 5, 2013, Pages 107~117
DOI : 10.9723/jksiis.2013.18.5.107
In order to enhance the performance of National R&D program, it is required not only the R&D funds and human resources, but also the composition of the research environment in which the researchers could fully concentrate on study. Particularly in Korea, executive burdens that arise in the course of the administration of research fund are frequently causing difficulties in concentrating on study. To remove this burden on financial management and maximize the efficiency of research funding, the government has implemented the central management system of the R&D fund. This study analyzed the moderating effects of the centralized management system of the R&D fund on the relationship between government fund and performance of the university research. Based on the analyzed result, this study concluded that the higher level of centralized management system of the R&D fund is implemented, the more influence on research outcomes grow. This study is significant to extend previous research point of view, as well as analyze the practical effect of government policies.