• Title, Summary, Keyword: 메모리 매핑

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Index block mapping for flash memory system (플래쉬 메모리 시스템을 위한 인덱스 블록 매핑)

  • Lee, Jung-Hoon
    • Journal of the Korea Society of Computer and Information
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    • v.15 no.8
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    • pp.23-30
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    • 2010
  • Flash memory is non-volatile and can retain data even after system is powered off. Besides, it has many other features such as fast access speed, low power consumption, attractive shock resistance, small size, and light-weight. As its price decreases and capacity increases, the flash memory is expected to be widely used in consumer electronics, embedded systems, and mobile devices. Flash storage systems generally adopt a software layer, called FTL. In this research, we proposed a new FTL mechanism for overcoming the major drawback of conventional block mapping algorithm. In addition to the block mapping table, a index block mapping table with a small size is used to indicate sector location. The proposed indexed block mapping algorithm by adding a small size. By the simulation result, the proposed FTL provides an enhanced speed than a conventional hybrid mapping algorithm by around 45% in average, and the requirement of mapping memory is also reduced by around 12%.

WADPM : Workload-Aware Dynamic Page-level Mapping Scheme for SSD based on NAND Flash Memory (낸드 플래시 메모리 기반 SSD를 위한 작업부하 적응형 동적 페이지 매핑 기법)

  • Ha, Byung-Min;Cho, Hyun-Jin;Eom, Young-Ik
    • Journal of KIISE:Computer Systems and Theory
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    • v.37 no.4
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    • pp.215-225
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    • 2010
  • The NAND flash memory based SSDs are considered to replace the existing HDDs. To maximize the I/O performance, SSD is composed of several NAND flash memories in parallel. However, to adopt the hybrid mapping scheme in SSD may cause degradation of the I/O performance. In this paper, we propose a new mapping scheme for the SSD called WADPM. WADPM loads only necessary mapping information into RAM and dynamically adjusts the size of mapping information in the RAM. So, WADPM avoids the shortcoming of page-level mapping scheme that requires too large mapping table. Performance evaluation using simulations shows that I/O performance of WADPM is 3.5 times better than the hybrid-mapping scheme and maximum size of mapping table of WADPM is about 50% in comparison with the page-level mapping scheme.

Adaptive Mapping Information Management Scheme for High Performance Large Sale Flash Memory Storages (고성능 대용량 플래시 메모리 저장장치의 효과적인 매핑정보 캐싱을 위한 적응적 매핑정보 관리기법)

  • Lee, Yongju;Kim, Hyunwoo;Kim, Huijeong;Huh, Taeyeong;Jung, Sanghyuk;Song, Yong Ho
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.3
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    • pp.78-87
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    • 2013
  • NAND flash memory has been widely used as a storage medium in mobile devices, PCs, and workstations due to its advantages such as low power consumption, high performance, and random accessability compared to a hard disk drive. However, NAND flash cannot support in-place update so that it is mandatory to erase the entire block before overwriting the corresponding page. In order to overcome this drawback, flash storages need a software support, named Flash Translation Layer. However, as the high performance mass NAND flash memory is getting widely used, the size of mapping tables is increasing more than the limited DRAM size. In this paper, we propose an adaptive mapping information caching algorithm based on page mapping to solve this DRAM space shortage problem. Our algorithm uses a mapping information caching scheme which minimize the flash memory access frequency based on the analysis of several workloads. The experimental results show that the proposed algorithm can increase the performance by up to 70% comparing with the previous mapping information caching algorithm.

HAMM(Hybrid Address Mapping Method) for Increasing Logical Address Mapping Performance on Flash Translation Layer of SSD (SSD 플래시 변환 계층 상에서 논리 주소 매핑의 성능 향상을 위한 HAMM(Hybrid Address Mapping Method))

  • Lee, Ji-Won;Roh, Hong-Chan;Park, Sang-Hyun
    • The KIPS Transactions:PartD
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    • v.17D no.6
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    • pp.383-394
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    • 2010
  • Flash memory based SSDs are currently being considered as a promising candidate for replacing hard disks due to several superior features such as shorter access time, lower power consumption and better shock resistance. However, SSDs have different characteristics from hard disk such as difference of unit and time for read, write and erase operation and impossibility for over-writing. Because of these reasons, SSDs have disadvantages on hard disk based systems, so FTL(Flash Translation Layer) is designed to increase SSDs' efficiency. In this paper, we propose an advanced logical address mapping method for increasing SSDs' performance, which is named HAMM(Hybrid Address Mapping Method). HAMM addresses drawbacks of previous block-mapping method and super-block-mapping method and takes advantages of them. We experimented our method on our own SSDs simulator. In the experiments, we confirmed that HAMM uses storage area more efficiently than super-block-mapping method, given the same buffer size. In addition, HAMM used smaller memory than block-mapping method to construct mapping table, demonstrating almost same performance.

Comparison of Compression Schemes for Real-Time 3D Texture Mapping (실시간 3차원 텍스춰 매핑을 위한 압축기법의 성능 비교)

  • Park, Gi-Ju;Im, In-Seong
    • Journal of the Korea Computer Graphics Society
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    • v.6 no.4
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    • pp.35-42
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    • 2000
  • 3D texture mapping generates highly natural visual effects in which objects appear carved from lumps of materials rather than laminated with thin sheets as in 2D texture mapping. Storing 3D texture images in a table for fast mapping computations, instead of evaluating procedures on the fly, however, has been considered impractical due to the extremely high memory requirement. Recently, a practical real-time 3D texture mapping technique was proposed in [11], where they attempt to resolve the potential texture memory problem by compressing 3D textures using a wavelet-based encoding method. In this paper, we consider two other encoding schemes that could also be applied to the compression-based 3D texture mapping. In particular, we extend the vector quantization and FXT1 for 3D texture compression, and compare their performance with the wavelet-based encoding scheme.

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Design of an Efficient FTL Algorithm for Flash Memory Accesses Using Sector-level Mapping (섹터 매핑 기법을 적용한 효율적인 FTL 알고리듬 설계)

  • Yoon, Tae-Hyun;Kim, Kwang-Soo;Hwang, Sun-Young
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.12B
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    • pp.1418-1425
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    • 2009
  • This paper proposes a novel FTL (Flash Translation Layer) algorithm based on sector-level mapping to reduce the number of total erase operations in flash memory accesses. The proposed algorithm can reduce the number of erase operations by utilizing the sector-level mapping table when writing data at flash memory. Sector-level mapping technique reduces flash memory access time and extendsthe life time of the flash memory. In the algorithm, wear-leveling is implemented by selecting victim blocks having the minimal number of erase operations, when empty spaces for write are not available. To evaluate the performance of the proposed FTL algorithm, experiments were performed on several applications, such as MP3 players, MPEG players, web browsers and document editors. The proposed algorithm reduces the number of erase operations by 72.4% and 61.9%, when compared with well-known BAST and FAST algorithms, respectively.

Efficient FTL Mapping Management for Multiple Sector Size-based Storage Systems with NAND Flash Memory (다중 섹터 사이즈를 지원하는 낸드 플래시 메모리 기반의 저장장치를 위한 효율적인 FTL 매핑 관리 기법)

  • Lim, Seung-Ho;Choi, Min
    • Journal of KIISE:Computing Practices and Letters
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    • v.16 no.12
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    • pp.1199-1203
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    • 2010
  • Data transfer between host system and storage device is based on the data unit called sector, which can be varied depending on computer systems. If NAND flash memory is used as a storage device, the variant sector size can affect storage system performance since its operation is much related to sector size and page size. In this paper, we propose an efficient FTL mapping management scheme to support multiple sector size within one NAND flash memory based storage device, and analyze the performance effect and management overhead. According to the proposed scheme, the management overhead of proposed FTL management is lower than conventional scheme when various sector sizes are configured in computer systems, while performance is less degraded in comparison with single sector size support system.

Memory Reduction Method of DIT-based IFFT Bit-Reversal (DIT 기반 IFFT의 Bit-Reversal 메모리 감소 기법)

  • Kim, Jun-Ho;Piao, Zheyan;Cho, Kyung-Ju;Chung, Jin-Gyun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.52 no.5
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    • pp.66-73
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    • 2015
  • IFFT is one of the key components in OFDM-based communication systems. In this paper, we propose a new memory efficient IFFT design method for OFDM-based communication systems, based on a mapping of three IFFT input signals which consist of modulated data, pilot and null signals. The proposed method focuses on reducing the memory size in the bit-reversal block which requires the largest number of memory cells in IFFT architectures. To reduce the memory size, we propose a selection mapping method based on decimation-in-time (DIT) algorithm. It is shown that the proposed method achieves a memory reduction of about 50% compared to conventional methods.

Index Management Method using Page Mapping Log in B+-Tree based on NAND Flash Memory (NAND 플래시 메모리 기반 B+ 트리에서 페이지 매핑 로그를 이용한 색인 관리 기법)

  • Kim, Seon Hwan;Kwak, Jong Wook
    • Journal of the Korea Society of Computer and Information
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    • v.20 no.5
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    • pp.1-12
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    • 2015
  • NAND flash memory has being used for storage systems widely, because it has good features which are low-price, low-power and fast access speed. However, NAND flash memory has an in-place update problem, and therefore it needs FTL(flash translation layer) to run for applications based on hard disk storage. The FTL includes complex functions, such as address mapping, garbage collection, wear leveling and so on. Futhermore, implementation of the FTL on low-power embedded systems is difficult due to its memory requirements and operation overhead. Accordingly, many index data structures for NAND flash memory have being studied for the embedded systems. Overall performances of the index data structures are enhanced by a decreasing of page write counts, whereas it has increased page read counts, as a side effect. Therefore, we propose an index management method using a page mapping log table in $B^+$-Tree based on NAND flash memory to decrease page write counts and not to increase page read counts. The page mapping log table registers page address information of changed index node and then it is exploited when retrieving records. In our experiment, the proposed method reduces the page read counts about 61% at maximum and the page write counts about 31% at maximum, compared to the related studies of index data structures.

High Performance Rendering system using a Rasterizer Merged Frame Buffer (래스터라이저-프레임버퍼 혼합 설계기술을 이용한 고성능 랜더링 시스템 설계)

  • 최춘자;박우찬;한탁돈
    • Proceedings of the Korean Information Science Society Conference
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    • pp.9-11
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    • 1999
  • 3차원 그래픽 랜더링 파이프라인(3D Graphics Rendering Pipeline)은 크게 지오메트리 프로세싱(Geometry Processing)과 레스터라이제이션(Rasterization)으로 구성되어 있다. 본 논문에서는 래스터라이저와 프레임버퍼사이의 대역폭으로 인한 병목점을 분석하고, 그 한계를 극복해 낼 수 있도록 프로세서 메모리 집적구조를 이용하여 랜더링 시스템을 설계, 성능 분석한다. 프레임버퍼의 집적으로 인한 메모리 대역폭을 이용하기 위해, 각 픽셀 처리에 필요한 로직을 포함하는 SIMD 타입의 픽셀 처리 프로세서가 메모리 어레이와 밀결합(tightly coupled)된다. 제안하는 구조는 래스터라이저 로직과 프레임 버퍼가 단일 칩으로 구성되었고, 텍스쳐 매핑, 범프 매핑, 안티알리아싱, 깊이 버퍼를 지원하며 초당 5백만 이상의 삼각형을 처리할 수 있는 고성능 랜더링 시스템이다.

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