• Title, Summary, Keyword: 아날로그/디지털 변환기

Search Result 200, Processing Time 0.04 seconds

A 10-bit 10-MS/s Asynchronous SAR analog-to-digital converter with digital-to-analog converter using MOM capacitor (MOM 커패시터를 사용한 디지털-아날로그 변환기를 가진 10-bit 10-MS/s 비동기 축차근사형 아날로그-디지털 변환기)

  • Jeong, Yeon-Ho;Jang, Young-Chan
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.18 no.1
    • /
    • pp.129-134
    • /
    • 2014
  • This paper presents a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) which consists of a digital-to-analog converter (DAC), a SAR logic, and a comparator. The designed asynchronous SAR ADC with a rail-to-rail input range uses a binary weighted DAC using metal-oxide-metal (MOM) capacitor to improve sampling rate. The proposed 10-bit 10-MS/s asynchronous SAR ADC is fabricated using a 0.18-${\mu}m$ CMOS process and its active area is $0.103mm^2$. The power consumption is 0.37 mW when the voltage of supply is 1.1 V. The measured SNDR are 54.19 dB and 51.59 dB at the analog input frequency of 101.12 kHz and 5.12 MHz, respectively.

Analog-to-Digital Conveter Using Synchronized Clock with Digital Conversion Signal (디지털 변환신호와 동기화된 클록을 사용하는 아날로그-디지털 변환기)

  • Choi, Jin-Ho;Jang, Yun-Seok
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • /
    • pp.522-523
    • /
    • 2017
  • Analog-to-Digital converter is designed using a current conveyor circuit and a time-to-digital converter. The analog voltage is sampled using the current conveyor circuit and then the voltage is converted to time information by the discharge of the sampling voltage. The time information is converted to digital value by the counter-type time-to-digital converter. In order to reduce the converted error the clock is synchronized with the time information pulse.

  • PDF

A 10-bit 10-MS/s 0.18-㎛ CMOS Asynchronous SAR ADC with split-capacitor based differential DAC (분할-커패시터 기반의 차동 디지털-아날로그 변환기를 가진 10-bit 10-MS/s 0.18-㎛ CMOS 비동기 축차근사형 아날로그-디지털 변환기)

  • Jeong, Yeon-Ho;Jang, Young-Chan
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.17 no.2
    • /
    • pp.414-422
    • /
    • 2013
  • This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of $140{\times}420{\mu}m^2$ is fabricated using a 0.18-${\mu}m$ CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.

A 2.5V 0.25㎛ CMOS Temperature Sensor with 4-bit SA ADC (4-비트 축차근사형 아날로그-디지털 변환기를 내장한 2.5V 0.25㎛ CMOS 온도 센서)

  • Kim, Mungyu;Jang, Young-Chan
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.17 no.2
    • /
    • pp.378-384
    • /
    • 2013
  • In this paper, a CMOS temperature sensor is proposed to measure the internal temperature of a chip. The temperature sensor consists of a proportional-to-absolute-temperature (PTAT) circuit for a temperature sensing part and a 4-bit analog-to-digital converter (ADC) for a digital interface. The PTAT circuit with the compact area is designed by using a vertical PNP architecture in the CMOS process. To reduce sensitivity of temperature variation in the digital interface circuit of the proposed temperature sensor, a 4-bit successive approximation (SA) ADC using the minimum analog circuits is used. It uses a capacitor-based digital-to-analog converter and a time-domain comparator to minimize power consumption. The proposed temperature sensor was fabricated by using a $0.25{\mu}m$ 1-poly 6-metal CMOS process with a 2.5V supply, and its operating temperature range is from 50 to $150^{\circ}C$. The area and power consumption of the fabricated temperature sensor are $130{\times}390{\mu}m^2$ and $868{\mu}W$, respectively.

A 10-bit CMOS Time-Interpolation Digital-to-Analog Converter (10-비트 CMOS 시간-인터폴레이션 디지털-아날로그 변환기)

  • Kim, Myngyu;Jang, Young-Chan
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • /
    • pp.225-228
    • /
    • 2012
  • In this paper, a 10-bit digital-to-analog converter (DAC) with small area is proposed. The 10-bit DAC consists of a 8-bit decoder, a 2-bit time-interpolator, and a buffer amplifier. The proposed time-interpolation is achieved by controlling the charging time through a low-pass filter composed of a resistor and a capacitor. To implement the accurate time-interpolator, a control pulse generator using a replica circuit is proposed to minimize the effect of the process variation. The proposed 10-bit Time-Interpolation DAC occupies 61 % of the conventional 10-bit resistor-string DAC. The proposed DAC is designed using a $0.35{\mu}m$ CMOS process with a 3.3 V supply. The simulated DNL and INL are +0.15/-0.21 LSB and +0.15/-0.16 LSB, respectively.

  • PDF

Active-RC Channel Selection Filter with 40MHz Bandwidth and Improved Linearity (개선된 선형성을 가지는 R-2R 기반 5-MS/s 10-비트 디지털-아날로그 변환기)

  • Jeong, Dong-Gil;Park, Sang-Min;Hwang, Yu-Jeong;Jang, Young-Chan
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.19 no.1
    • /
    • pp.149-155
    • /
    • 2015
  • This paper proposes 5-MS/s 10-bit digital-to-analog converter(DAC) with the improved linearity. The proposed DAC consists of a 10-bit R-2R-based DAC, an output buffer using a differential voltage amplifier with rail-to-rail input range, and a band-gap reference circuit for the bias voltage. The linearity of the 10-bit R-2R DAC is improved as the resistor of 2R is implemented by including the turn-on resistance of an inverter for a switch. The output voltage range of the DAC is determined to be $2/3{\times}VDD$ from an rail-to-rail output voltage range of the R-2R DAC using a differential voltage amplifier in the output buffer. The proposed DAC is implemented using a 1-poly 8-metal 130nm CMOS process with 1.2-V supply. The measured dynamic performance of the implemented DAC are the ENOB of 9.4 bit, SNDR of 58 dB, and SFDR of 63 dBc. The measured DNL and INL are less than +/-0.35 LSB. The area and power consumption of DAC are $642.9{\times}366.6{\mu}m^2$ and 2.95 mW, respectively.

Digitally Controlled Synchronous Buck Converter (디지털 제어를 적용한 동기식 강압형 직류-직류 변환기)

  • Kim, Dong-Myung;Choi, Seok-Jae;Choi, Byung-Cho
    • Proceedings of the KIPE Conference
    • /
    • /
    • pp.347-348
    • /
    • 2010
  • 본 논문에서는 기본적인 직류-직류 변환기 중 하나인 동기식 강압형 직류-직류 변화기를 디지털 제어로 구현함으로서 아날로그 제어기를 디지털 제어기로 변환 하는 과정에 관하여 설명한다. 먼저 전원단의 소신호 특성을 해석하여 제어대 출력전압의 전달함수를 찾아내고, 이것을 토대로 아날로그 제어기를 설계 하여 Simulink를 통하여 시뮬레이션을 수행하고, 설계된 아날로그 제어기를 바탕으로 Matlab을 이용한 Emulation 기법을 사용하여 디지털 제어기를 설계 한다. DSP(TMS320F28335)를 사용한 동기식 강압형 직류-직류 변환기에 설계된 디지털 제어기를 적용하여 안정도와 부하변동에 따른 응답 특성을 확인 한다.

  • PDF

A CMOS Digital-to-Analog Converter to Apply a Newly-Developed Digital-to-Analog Conversion Algorithm (새로운 디지털-아날로그 변환알고리즘을 적용한 CMOS 디지털-아날로그 변환기)

  • 송명호
    • Journal of the Korean Institute of Telematics and Electronics C
    • /
    • v.35C no.9
    • /
    • pp.57-63
    • /
    • 1998
  • This paper describes a CMOS digital-to-analog converter to apply a newly-developed digital-to-analog conversion algorithm. The CMOS digital-to-analog converter has been designed by using 1.2$\mu\textrm{m}$ MOSIS SCMOS parameter and simulated for the performance. The simulated results have shown that the digital-to-analog converter has 200MHz of the maximum conversion rate, 7.41mW of the DC power consumption, and ${\pm}$0.08LSB of INL and ${\pm}$0.098LSB of DNL in 8-b.

  • PDF

Low-power Analog-to-Digital Converter for video signal processing (비디오 신호처리용 저전력 아날로그 디지털 변환기)

  • 조성익;손주호;김동용
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.24 no.8A
    • /
    • pp.1259-1264
    • /
    • 1999
  • In this paper, the High-speed, Low-power Analog-Digital Conversion Archecture is porposed using the Pipelined archecture for High-speed conversion rate and the Successive-Approximation archecture for Low-power consumption. This archecture is the Successive-Approximation archecture using Pipelined Comparator array to change reference voltage during Holding Time. The Analog-to-Digital Converter for video processing is designed using 0.8${\mu}{\textrm}{m}$ CMOS tchnology. When an 6-bit 10MS/s Analog-to-Digital Converter is simulatined, the INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 37dB at a sampling rate of 10MHz with 100KHz sine input signal. The power consumption is 1.46mW at 10MS/s. When an 8-bit 10MS/s Analog-to Digital Converter is simulatined, the INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 41dB at a sampling rate of 100MHz with 100KHz sine input signal. The power consumption is 4.14m W at 10MS/s.

  • PDF

Design of a Low power Analog-to-Digital Converter with 8bit 10MS/s (8비트 10MS/s 저전력 아날로그-디지털 변환기 설계)

  • 손주호;이근호;설남오;김동용
    • The Journal of the Acoustical Society of Korea
    • /
    • v.17 no.7
    • /
    • pp.74-78
    • /
    • 1998
  • 본 논문에서는 고속의 변환속도를 갖는 파이프라인드 방식과 저전력 특성을 갖는 축차 비교 방식 구조를 혼용하여 고속, 저전력 아날로그-디지털 변환기를 설계하였다. 제안 된 구조는 축차 비교 방식의 변환에서 비교기를 파이프라인드 구조로 연결하여 홀드된 주기 에 비교기의 기준 전위를 전 비교기의 출력값에 의해 변환하도록 하여 고속 동작이 가능하 도록 하였다. 제안된 구조에 의해 8비트 아날로그 디지털 변환기를 0.8㎛ CMOS공정으로 HSPICE를 이용하여 시뮬레이션한 결과, INL/DNL은 각각 ±0.5/±1이었으며, 100kHz 사인 입력 신호를 10MS/s로 샘플링 하여 DFT측정 결과 SNR은 41dB를 얻을 수 있었다. 10MS/s의 변환 속도에서 전력 소모는 4.14mW로 측정되었다.

  • PDF