• Title, Summary, Keyword: 주파수 소요량 추정

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Bandwidth Requirement Estimation Method for Future Wireless Railway Communication Systems (차세대 철도통합무선망을 위한 주파수 소요량 계산방법)

  • Jeong, Minwoo;Yoon, Hyungoo;Park, Duk-Kyu;Kim, Kyung-Hee;Lee, Sukjin
    • Journal of the Korean Society for Railway
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    • v.16 no.6
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    • pp.540-550
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    • 2013
  • The Future Wireless Railway Communication System(FWRCS) has attracted attention for the various advantages of such a system like efficient management, precise periodicity of operation and speedy travel. Related to it, the area of bandwidth requirement estimation for the FWRCS is being researched actively because there is a great need for accurate bandwidth distribution. In this paper, sophisticated bandwidth requirement estimation method for FWRCS is proposed by modifying ITU-R M.1390. With this method, the expected frequency requirements for the present, for five years from now, and for 10 years from now can be calculated by applying the data gathered from the actual field.

Frequency Synchronization Algorithm of OFDM System for Fine Frequency Offset Compensation (미세 주파수 옵셋 보상을 위한 OFDM시스템의 주파수 동기 알고리즘)

  • 서재현;한동석;김기범
    • Proceedings of the IEEK Conference
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    • pp.55-58
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    • 2000
  • 본 논문에서는 제한된 통신 채널의 대역에서 주파수 효율이 높은 OFDM 시스템을 위한 반송파 주파수 동기 알고리즘을 제안한다. OFDM 시스템에서의 반송파 주파수 옵셋은 부반송파 간격의 정수배와 소수배로 나누어진다 소수배 주파수 옵셋이 ± 0.5 근처의 값을 가질 경우에는 정확한 정수배 주파수 옵셋 추정이 어렵고 반송파 동기 PLL이 소수배 주파수 옵셋을 추적하는데 많은 시간이 소요된다. 제안한 알고리즘은 정수배 주파수 옵셋을 제거하기 위해 2개의 심볼 만을 이용하고 다중경로 패널에서도 정확한 정수배 주파수 옵셋의 추정이 가능하다 또한, 소수배 주파수 옵셋이 ± 0.5 근처의 값을 가질 경우 적은 계산량으로 주파수 옵셋을 ± 0.1 이내로 보상할 수 있다.

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A New Hardware Architecture of High-Speed Motion Estimator for H.264 Video CODEC (H.264 비디오 코덱을 위한 고속 움직임 예측기의 하드웨어 구조)

  • Lim, Jeong-Hun;Seo, Young-Ho;Choi, Hyun-Jun;Kim, Dong-Wook
    • Journal of Broadcast Engineering
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    • v.16 no.2
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    • pp.293-304
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    • 2011
  • In this paper, we proposed a new hardware architecture for motion estimation (ME) which is the most time-consuming unit among H.264 algorithms and designed to the type of intellectual property (IP). The proposed ME hardware consists of buffer, processing unit (PU) array, SAD (sum of absolute difference) selector, and motion vector (MVgenerator). PU array is composed of 16 PUs and each PU consists of 16 processing elements (PUs). The main characteristics of the proposed hardware are that current and reference frames are re-used to reduce the number of access to the external memory and that there is no clock loss during SAD operation. The implemented ME hardware occupies 3% hardware resources of StatixIII EP3SE80F1152C2 which is a FPGA of Altera Inc. and can operate at up to 446.43MHz. Therefore it can process up to 50 frames of 1080p in a second.