• Title, Summary, Keyword: 캐쉬 분할기법

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Web Cache Partition Strategy based on File Type (파일 타입에 의한 웹 캐쉬 분할기법)

  • 오윤주;한지영;이은화;윤성대
    • Proceedings of the Korean Information Science Society Conference
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    • pp.31-33
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    • 2003
  • 최근 웹 사용자의 수가 급격히 증가하고 있다. 이로 인해 인터넷 객체의 캐슁 기법이 매우 중요한 문제가 되었다. 웹 캐쉬는 전통적인 캐쉬와는 달리 다양한 종류와 크기를 가진 개체를 다루어야 하므로 웹 캐쉬에서 보다 나은 적중률을 얻기 위해 털러 접근 방법들이 연구되고 있다 그에 대한 방법으로 동적인 웹 환경을 고려하면서 캐쉬 공간 관리의 효율성을 높이기 위한 분할캐쉬 접근 방법, 또한 웹 캐쉬의 성능향상에 중요한 역할을 하는 교체 알고리즘에 대한 연구도 계속 진행되어 왔다. 본 논문에서는 캐쉬를 파일 타입에 기반을 둔 클래스별로 분할하고, 각각의 클래스에 효율적인 교체 알고리즘을 사용한다. 그리고 사용자의 객체 요구 변화에 대응하기 위해 일정 간격으로 클래스별 분할비를 갱신한다.

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Energy-aware Instruction Cache Design using Partitioning (분할 기법을 이용한 저전력 명령어 캐쉬 설계)

  • Kim, Jong-Myon;Jung, Jae-Wook;Kim, Cheol-Hong
    • Journal of KIISE:Computing Practices and Letters
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    • v.13 no.5
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    • pp.241-251
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    • 2007
  • Energy consumption in the instruction cacheaccounts for a significant portion of the total processor energy consumption. Therefore, reducing energy consumption in the instruction cache is important in designing embedded processors. This paper proposes a method for reducing dynamic energy consumption in the instruction cache by partitioning it to smaller (less energy-consuming) sub-caches. When a request comes into the proposed cache, only one sub-cache is accessed by utilizing the locality of applications. By contrast, the other sub-caches are not accessed, leading todynamic energy reduction. In addition, the proposed cache reduces dynamic energy consumption by eliminating the energy consumed in tag matching. We evaluated the energy efficiency by running cycle accurate simulator, SimpleScalar. with power parameters obtained from CACTI. Simulation results show that the proposed cache reduces dynamic energy consumption by $37%{\sim}60%$ compared to the traditional direct-mapped instruction cache.

Processor Design Technique for Low-Temperature Filter Cache (필터 캐쉬의 저온도 유지를 위한 프로세서 설계 기법)

  • Choi, Hong-Jun;Yang, Na-Ra;Lee, Jeong-A;Kim, Jong-Myon;Kim, Cheol-Hong
    • Journal of the Korea Society of Computer and Information
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    • v.15 no.1
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    • pp.1-12
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    • 2010
  • Recently, processor performance has been improved dramatically. Unfortunately, as the process technology scales down, energy consumption in a processor increases significantly whereas the processor performance continues to improve. Moreover, peak temperature in the processor increases dramatically due to the increased power density, resulting in serious thermal problem. For this reason, performance, energy consumption and thermal problem should be considered together when designing up-to-date processors. This paper proposes three modified filter cache schemes to alleviate the thermal problem in the filter cache, which is one of the most energy-efficient design techniques in the hierarchical memory systems : Bypass Filter Cache (BFC), Duplicated Filter Cache (DFC) and Partitioned Filter Cache (PFC). BFC scheme enables the direct access to the L1 cache when the temperature on the filter cache exceeds the threshold, leading to reduced temperature on the filter cache. DFC scheme lowers temperature on the filter cache by appending an additional filter cache to the existing filter cache. The filter cache for PFC scheme is composed of two half-size filter caches to lower the temperature on the filter cache by reducing the access frequency. According to our simulations using Wattch and Hotspot, the proposed partitioned filter cache shows the lowest peak temperature on the filter cache, leading to higher reliability in the processor.

Core-aware Cache Replacement Policy for Reconfigurable Last Level Cache (재구성 가능한 라스트 레벨 캐쉬 구조를 위한 코어 인지 캐쉬 교체 기법)

  • Son, Dong-Oh;Choi, Hong-Jun;Kim, Jong-Myon;Kim, Cheol-Hong
    • Journal of the Korea Society of Computer and Information
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    • v.18 no.11
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    • pp.1-12
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    • 2013
  • In multi-core processors, Last Level Cache(LLC) can reduce the speed gap between the memory and the core. For this reason, LLC has big impact on the performance of processors. LLC is composed of shared cache and private cache. In computer architecture community, most researchers have mainly focused on the management techniques for shared cache, while management techniques for private cache have not been widely researched. In conventional private LLC, memory is statically assigned to each core, resulting in serious performance degradation when the workloads are not fairly distributed. To overcome this problem, this paper proposes the replacement policy for managing private cache of LLC efficiently. As proposed core-aware cache replacement policy can reconfigure LLC dynamically, hit rate of LLC is increases drastically. Moreover, proposed policy uses 2-bit saturating counters to improve the performance. According to our simulation results, the proposed method can improve hit rates by 9.23% and reduce the access time by 12.85% compared to the conventional method.

Low-Power Data Cache Architecture and Microarchitecture-level Management Policy for Multimedia Application (멀티미디어 응용을 위한 저전력 데이터 캐쉬 구조 및 마이크로 아키텍쳐 수준 관리기법)

  • Yang Hoon-Mo;Kim Cheong-Gil;Park Gi-Ho;Kim Shin-Dug
    • The KIPS Transactions:PartA
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    • v.13A no.3
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    • pp.191-198
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    • 2006
  • Today's portable electric consumer devices, which are operated by battery, tend to integrate more multimedia processing capabilities. In the multimedia processing devices, multimedia system-on-chips can handle specific algorithms which need intensive processing capabilities and significant power consumption. As a result, the power-efficiency of multimedia processing devices becomes important increasingly. In this paper, we propose a reconfigurable data caching architecture, in which data allocation is constrained by software support, and evaluate its performance and power efficiency. Comparing with conventional cache architectures, power consumption can be reduced significantly, while miss rate of the proposed architecture is very similar to that of the conventional caches. The reduction of power consumption for the reconfigurable data cache architecture shows 33.2%, 53.3%, and 70.4%, when compared with direct-mapped, 2-way, and 4-way caches respectively.

디스크를 공유하는 다중 시스템 상에서 캐쉬 일관성 유지를 위한 동적 PCA 할당

  • 김신희;류명춘;박정량
    • Proceedings of the Korea Association of Information Systems Conference
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    • pp.137-144
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    • 1998
  • 데이터베이스 공유 시스템에서는 동일한 페이지가 여러 처리노드에 의해 동시에 캐싱 될 수 있으므로, 각 처리노드가 항상 최신의 내용을 참조하기 위해서는 캐싱 된 데이 터의 일관성이 유지되어야 한다. 본 논문에서는 로킹 오버헤드를 줄이기 위해 주사본 권한 을 이용하여 데이터베이스를 논리적으로 분할한 데이터베이스 공유 시스템 환경에서 필요한 캐쉬 일관성 기법들을 제안한다. 제안한 기법들인 DPCA_P와 DPCA_U는 PCA를 동적으로 할당하여 캐쉬 일관성을 위해 소요되는 메시지 전송량과 디스크 입출력 오버헤드를 줄임으 로써 성능을 향상시키며, 데이터베이스 부하가 동적으로 변하는 경우에도 효율적으로 동작 한다는 장점을 갖는다.

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1pCSB+ - tree: An Enhanced Main Memory Index Structure Employing Level Prefetching Technique (1pCSB+ - 트리: 레벨 프리페칭 기법을 이용하는 향상된 주기억장치 상주형 색인구조)

  • Hong, Hyun-Taek;Pee, Jun-Il;Song, Seok-Il;Yoo, Jae-Soo
    • Proceedings of the Korea Information Processing Society Conference
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    • pp.1753-1756
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    • 2002
  • 주기억장치 상주형 색인구조에서는 2차 캐쉬 실패가 성능에 매우 큰 영향을 미친다. 기존에 제안된 주기억장치 상주형 색인구조들은 2차 캐쉬 실패를 고려하긴 했지만 여전히 트리의 각 레벨을 접근할 때는 2차 캐쉬실패가 발생한다. 본 논문에서는 이러한 문제점을 인식하고 트리 순회시 각 레벨을 방문할 때도 캐쉬 실패가 발생하지 않는 주기억장치 색인구조를 제안한다. 제안하는 색인구조는 다음 레벨에서 방문할 가능성이 있는 노드들을 프리페칭하여 다음 레벨을 방문할 때도 캐쉬 실패가 발생하지 않도록 한다. 또한, 기본적인 구조는 노드그룹 개념을 이용하여 노드의 팬-아웃을 증가시키는 CSB+-트리에 기반하지만 CSB+-트리의 다점인 분할 비용의 증가문제를 해결하기 위한 방법을 제안한다. 시뮬레이션을 통해 기존의 색인구조와 비교하여 제안하는 색인구조의 우수성을 보인다.

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New Data Buffering Scheme for News On Demand (NOD 데이터를 위한 새로운 버퍼링 기법)

  • 박용운;백건효;서원일;김영주;정기동
    • Proceedings of the Korean Society of Broadcast Engineers Conference
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    • pp.173-179
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    • 1997
  • 본 연구에서는 실시간 데이터와 비 실시간 데이터가 복합적으로 존재하는 뉴스 데이터에 적합하도록 버퍼 캐쉬를 실시간 데이터와 비 실시간 데이터 영역으로 분할 한 후, 로그 데이터를 이용하여 접근 가능성이 높은 실시간 뉴스데이터를 프리팻칭하여 둠으로써 실시간 뉴스 데이터의 운영을 효과적으로 할 수 있는 새로운 버퍼 캐쉬 알고리즘을 제안한다. 이 방식을 이용함으로써 전체 뉴스 요청 건수 중 30% 이상의 요청 건수들이 디스크를 접근하지 않고 버퍼의 데이터를 접근함으로써 버퍼링 기법을 사용하지 않은 경우보다 실시간 지원에 필요한 디스크 접근 수를 줄일 수 있다.

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Cache Coherency Schemes for Database Sharing Systems with Primary Copy Authority (주사본 권한을 지원하는 공유 데이터베이스 시스템을 위한 캐쉬 일관성 기법)

  • Kim, Shin-Hee;Cho, Haeng-Rae;Kim, Byeong-Uk
    • The Transactions of the Korea Information Processing Society
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    • v.5 no.6
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    • pp.1390-1403
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    • 1998
  • Database sharing system (DSS) refers to a system for high performance transaction processing. In DSS, the processing nodes are locally coupled via a high speed network and share a common database at the disk level. Each node has a local memory, a separate copy of operating system, and a DB'\fS. To reduce the number of disk accesses, the node caches database pages in its local memory buffer. However, since multiple nodes may be simultaneously cached a page, cache consistency must be cnsured so that every node can always access the'latest version of pages. In this paper, we propose efficient cache consistency schemes in DSS, where the database is logically partitioned using primary copy authority to reduce locking overhead, The proposed schemes can improve performance by reducing the disk access overhead and the message overhead due to maintaining cache consistency, Furthermore, they can show good performance when database workloads are varied dynamically.

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Making Cache-Conscious CCMR-trees for Main Memory Indexing (주기억 데이타베이스 인덱싱을 위한 CCMR-트리)

  • 윤석우;김경창
    • Journal of KIISE:Databases
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    • v.30 no.6
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    • pp.651-665
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    • 2003
  • To reduce cache misses emerges as the most important issue in today's situation of main memory databases, in which CPU speeds have been increasing at 60% per year, and memory speeds at 10% per year. Recent researches have demonstrated that cache-conscious index structure such as the CR-tree outperforms the R-tree variants. Its search performance can be poor than the original R-tree, however, since it uses a lossy compression scheme. In this paper, we propose alternatively a cache-conscious version of the R-tree, which we call MR-tree. The MR-tree propagates node splits upward only if one of the internal nodes on the insertion path has empty room. Thus, the internal nodes of the MR-tree are almost 100% full. In case there is no empty room on the insertion path, a newly-created leaf simply becomes a child of the split leaf. The height of the MR-tree increases according to the sequence of inserting objects. Thus, the HeightBalance algorithm is executed when unbalanced heights of child nodes are detected. Additionally, we also propose the CCMR-tree in order to build a more cache-conscious MR-tree. Our experimental and analytical study shows that the two-dimensional MR-tree performs search up to 2.4times faster than the ordinary R-tree while maintaining slightly better update performance and using similar memory space.