• Title, Summary, Keyword: 캐시실패

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Low-Power Cache Design by using Locality Buffer and Address Compression (지역 버퍼와 주소 압축을 통한 저전력 캐시 설계)

  • Kwak, Jong Wook
    • Journal of the Korea Society of Computer and Information
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    • v.18 no.9
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    • pp.11-19
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    • 2013
  • Most modern computer systems employ cache systems in order to alleviate the access time gap between processor and memory system. The power dissipated by the cache systems becomes a significant part of the total power dissipated by whole microprocessor chip. Therefore, power reduction in the cache system becomes one of the important issues. Partial tag cache is the system for the least power consumption. The main power reduction for this method is due to the use of small partial tag matching, not full tag matching. In this paper, we first analyze the previous regular partial tag cache systems and propose a new address matching mechanism by using locality buffer and address compression. In simulation results, the proposed model shows 18% power reduction in average, still providing same performance level, compared to regular cache.

KDBcs-Tree : An Efficient Cache Conscious KDB-Tree for Multidimentional Data (KDBcs-트리 : 캐시를 고려한 효율적인 KDB-트리)

  • Yeo, Myung-Ho;Min, Young-Soo;Yoo, Jae-Soo
    • Journal of KIISE:Databases
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    • v.34 no.4
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    • pp.328-342
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    • 2007
  • We propose a new cache conscious indexing structure for processing frequently updated data efficiently. Our proposed index structure is based on a KDB-Tree, one of the representative index structures based on space partitioning techniques. In this paper, we propose a data compression technique and a pointer elimination technique to increase the utilization of a cache line. To show our proposed index structure's superiority, we compare our index structure with variants of the CR-tree(e.g. the FF CR-tree and the SE CR-tree) in a variety of environments. As a result, our experimental results show that the proposed index structure achieves about 85%, 97%, and 86% performance improvements over the existing index structures in terms of insertion, update and cache-utilization, respectively.

Low-power Data Cache using Selective Way Precharge (데이터 캐시의 선택적 프리차지를 통한 에너지 절감)

  • Choi, Byeong-Chang;Suh, Hyo-Joong
    • The KIPS Transactions:PartA
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    • v.16A no.1
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    • pp.27-34
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    • 2009
  • Recently, power saving with high performance is one of the hot issues in the mobile systems. Various technologies are introduced to achieve low-power processors, which include sub-micron semiconductor fabrication, voltage scaling, speed scaling and etc. In this paper, we introduce a new method that reduces of energy loss at the data cache. Our methods take the benefits in terms of speed and energy loss using selective way precharging of way prediction with concurrent way selecting. By the simulation results, our method achieves 10.2% energy saving compared to the way prediction method, and 56.4% energy saving compared to the common data cache structure.

Empirical Modeling for Cache Miss Rates in Multiprocessors (다중 프로세서에서의 캐시접근 실패율을 위한 경험적 모델링)

  • Lee, Kang-Woo;Yang, Gi-Joo;Park, Choon-Shik
    • Journal of KIISE:Computer Systems and Theory
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    • v.33 no.1_2
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    • pp.15-34
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    • 2006
  • This paper introduces an empirical modeling technique. This technique uses a set of sample results which are collected from a few small scale simulations. Empirical models are developed by applying a couple of statistical estimation techniques to these samples. We built two types of models for cache miss rates in Symmetric Multiprocessor systems. One is for the changes of input data set size while the specification of target system is fixed. The other is for the changes of the number of processors in target system while the input data set size is fixed. To develop accurate models, we built individual model for every kind of cache misses for each shared data structure in a program. The final model is then obtained by integrating them. Besides, combined use of Least Mean Squares and Robust Estimations enhances the quality of models by minimizing the distortion due to outliers. Empirical modeling technique produces extremely accurate models without analysis on sample data. In addition, since only snail scale simulations are necessary, once a set of samples can be collected, empirical method can be adopted in any research areas. In 17 cases among 24 trials, empirical models present extremely low prediction errors below $1\%$. In the remaining cases, the accuracy is excellent, as well. The models sustain high quality even when the behavioral characteristics of programs are irregular and the number of samples are barely enough.

An Efficient Replication Strategy in Unstructured Peer-to-Peer Networks (비구조적인 피어-투-피어 네트워크상에서 효율적인 복제 기법)

  • Choi Wu-Rak;Lee Moon-Soo;Park Sung-Yong
    • Proceedings of the Korean Information Science Society Conference
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    • pp.271-273
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    • 2006
  • 초기의 비구조적인 피어-투-피어 방식은 플러딩(flooding) 방식의 검색 기법을 사용하는데, 이 기법은 통신비용이 매우 많이 소요되어 비효율적이다. 따라서 효율적인 검색 기법으로 임의 경로(random walk) 검색 방식이 제안되었다. 이 검색 기법은 메시지가 임의로 노드를 이동하기 때문에, 검색의 성공률이 낮다. 이를 보완하기 위하여 효율적인 복제기법이 요구된다. 현재 나와 있는 복제 기법은 여러 방법이 있으나, 모두 통신에 고비용을 요구한다. 따라서 복제 기법에서는 통신비용을 최소화하는 효율적인 복제 기법이 필요하다. 본 논문에서는 캐시를 사용하여 직접적인 데이터 통신비용을 최대로 줄이는 한편, 복제를 질의가 많이 도착하는 곳에 위치시켜 검색률의 저하를 막고, 잘못된 캐시 관리 기법을 통해 동적인 환경에서도 잘못된 캐시로 인한 검색의 실패를 최소할 수 있는 기법을 제안한다.

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Caching Scheme Considering Access Patterns in Graph Environments (그래프 환경에서 접근 패턴을 고려한 캐싱 기법)

  • Yoo, Seunghun;Kim, Minsoo;Bok, Kyoungsoo;Yoo, Jaesoo
    • Proceedings of the Korea Contents Association Conference
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    • pp.19-20
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    • 2017
  • 최근 소셜 미디어와 센서 장비의 기술의 발달로 그래프 데이터의 양이 급격히 증가 하였다. 그래프 데이터의 처리 과정에서 I/O 비용이 발생하여 데이터가 많아지면 병목현상으로 인해 데이터의 처리와 관리에 있어 성능에 한계가 발생한다. 이러한 문제를 해결하기 위해 데이터를 메모리에서 관리하는 캐시 기법에 대한 연구가 이루어 졌다. 본 논문에서는 서브그래프 데이터의 접근 패턴을 고려한 캐싱 기법을 제안한다. 그래프 환경에서 그래프 질의 이력을 통해 패턴을 찾고 질의 관리 테이블과 FP(frequent pattern)-Tree 통해 선별된 데이터를 메모리에 적재시킨다. 또한, 캐시 실패(cache miss)가 발생 하였을 때, 주변의 이웃 정점을 같이 메모리에 적재시킨다. 메모리가 가득 찰 경우 캐시 된 데이터를 퇴출시키는 교체 전략을 제안한다.

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Compact Field Remapping for Dynamically Allocated Structures (동적으로 할당된 구조체를 위한 압축된 필드 재배치)

  • Kim, Jeong-Eun;Han, Hwan-Soo
    • Journal of KIISE:Software and Applications
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    • v.32 no.10
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    • pp.1003-1012
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    • 2005
  • The most significant difference of embedded systems from general purpose systems is that embedded systems are allowed to use only limited resources including battery and memory. Especially, the number of applications increases which deal with multimedia data. In those systems with high data computations, the delay of memory access is one of the major bottlenecks hurting the system performance. As a result, many researchers have investigated various techniques to reduce the memory access cost. Most programs generally have locality in memory references. Temporal locality of references means that a resource accessed at one point will be used again in the near future. Spatial locality of references is that likelihood of using a resource gets higher if resources near it were just accessed. The latest embedded processors usually adapt cache memory to exploit these two types of localities. Processors access faster cache memory than off-chip memory, reducing the latency. In this paper we will propose the enhanced dynamic allocation technique for structure-type data in order to eliminate unused memory space and to reduce both the cache miss rate and the application execution time. The proposed approach aggregates fields from multiple records dynamically allocated and consecutively remaps them on the memory space. Experiments on Olden benchmarks show $13.9\%$ L1 cache miss rate drop and $15.9\%$ L2 cache miss drop on average, compared to the previously proposed techniques. We also find execution time reduced by $10.9\%$ on average, compared to the previous work.

Cache and Pipeline Architecture Improvement and Low Power Design of Embedded Processor (임베디드 프로세서의 캐시와 파이프라인 구조개선 및 저전력 설계)

  • Jung, Hong-Kyun;Ryoo, Kwang-Ki
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • pp.289-292
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    • 2008
  • This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of OpenRISC processor and a clock gating algorithm using ODC (Observability Don't Care) operation for a low-power processor. The branch prediction algorithm has a structure using BTB(Branch Target Buffer) and 4-way set associative cache has lower miss rate than direct-mapped cache. The clock gating algorithm reduces dynamic power consumption. As a result of estimation of performance and dynamic power, the performance of the OpenRISC processor using the proposed algorithm is improved about 8.9% and dynamic power of the processor using samsung $0.18{\mu}m$ technology library is reduced by 13.9%.

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Effect of Microkernel Structure on Cache Memory Performance (마이크로커널 구조가 캐시 메모리의 성능에 미치는 영향)

  • Chang, Moon-Seok;Koh, Kern
    • Journal of KIISE:Computer Systems and Theory
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    • v.27 no.1
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    • pp.68-80
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    • 2000
  • The modern software technology toward modularization has changed the cache accessing behavior dramatically. Many modern operating systems are also departing from the past monolithic structure toward the highly modularized structure referred to as microkernel. Microkernel-based operating systems are more portable and extensible, but are likely to have worse performance. This paper quantitatively analyzes the effect of microkernel structure on cache memory to identify the primary factor for its performance degradation. Through the experiment performed on a Intel Pentium Pro processor platform, we found that the microkernel structure suffers from remarkably higher misses for L1, L2 cache and TLB than the monolithic one does. We also found that the performance of a microkernel is more dependent on the efficiency of cache memory than IPC. Finally, we found that these results come from the effect of frequent context switches mainly caused by the structural feature of a microkernel.

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Design of a Multi-dimensional Index Structure based on Main Memory (주기억장치 상주형 다차원 색인 구조 설계)

  • 심정민;송석일;유재수
    • Proceedings of the Korean Information Science Society Conference
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    • pp.1-3
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    • 2003
  • 최근 중앙처리장치와 주기억장치간의 병목 현상에 의한 성능 저하를 극복하기 위해 캐시를 고려한 색인 구조들이 제안되었다. 이런 색인 구조들의 궁극적인 목표는 엔트리 크기를 줄여 팬-아웃(fan-out)을 증가시키고, 캐시 접근 실패를 최소화하여 시스템의 성능을 높이는 것이다. 엔트리의 크기를 줄이는 기법에 따라 기존의 색인 구조들을 두 가지로 구분할 수 있다. 하나는 좌표 값을 고정된 비트로 양자화 함으로써, MBR 키를 압축하는 것이다. 또 다른 하나는 MBR들의 각 좌표 값 중에 그들의 부모 MBR과 같지 않은 좌표 값만을 저장하는 것이다. 본 논문에서는 두 기법의 특성들을 적절히 합한 새로운 색인 구조를 제안하고, 기존에 제시된 두 접근법을 따르는 주기억장치 상주형 다차원 색인 구조를 다양한 환경에서 성능 평가한다. 또한, 기존의 색인 구조와 비교를 통해 제안하는 색인 구조의 우수성을 보인다.

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