• Title, Summary, Keyword: 캐시실패

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HTM-based transaction splitting technique for processing long transactions (long 트랜잭션 처리를 위한 HTM 기반 트랜잭션 분할 기법)

  • Kim, Hyeong-Jin;Ma, hyeon-guk;Lee, Jong-Chan;Chang, Jae-Woo
    • Proceedings of the Korea Contents Association Conference
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    • pp.29-30
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    • 2017
  • 최근 Hardware Transaction Memory (HTM)으로 트랜잭션을 처리하는 기술이 각광을 받고 있다. 그러나 HTM의 처리 실패 요인 중 하나는 캐시를 사용하여 트랜잭션을 처리하여 용량에 제한이 존재한다. 이러한 이유로 long 트랜잭션의 경우 용량을 초과하여 처리가 불가능한 경우가 빈번히 발생한다. 이를 해결하기 위해 본 논문에서는 long 트랜잭션 처리를 위한 HTM 기반 트랜잭션 분할 기법을 제안한다. 제안하는 기법은 먼저 HTM 으로 수행하여 캐시 용량을 초과하는 경우, long 트랜잭션을 다수의 트랜잭션으로 분할한다. 분할된 트랜잭션이 수행이 완료되면, 부분 커밋(commit)을 수행하고 이에 대한 정확성을 제공하기 위해 validation을 수행한다. 분할된 모든 트랜잭션의 수행이 완료되면 최종적인 커밋을 수행한다. 이를 통하여 기존 HTM 으로 처리하기 불가능한 long 트랜잭션을 속도가 우수한 HTM을 기반으로 효율적인 트랜잭션 처리가 가능하다.

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Remote Cache Replacement Policy based on Processor Locality (프로세서 지역성에 기반 한 원격 캐시 교체 정책)

  • 한상윤;곽종옥;전주식
    • Proceedings of the Korean Information Science Society Conference
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    • pp.4-6
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    • 2004
  • 본 논문에서는 원격 캐쉬를 추가시킨 분산 메모리 구조 다중 프로세서 시스템의 성능 향상을 위해 새로운 원격 캐쉬 교체 정색을 제안한다. 일반적으로 다중 계층 내포성(MLI)을 치키는 다중 계층 메모리 구조에서 LRU 교체 정책을 사용할 경우, 상위 계층 캐쉬의 LRU 정보와 하위 계층 캐쉬의 LRU 정보가 서로 상이함으로 인해 하위 계층 캐쉬에서의 교체가 상위 계층에서 사용 중인 캐처 라인의 교체를 발생시켜 전체 시스템의 성능을 저하시키는 원인이 된다. 이러한 LRU 캐쉬 교체 정책의 단점을 보완하고자 각 노드 당 프로세서들의 원격 메모리 접근 지역성을 이용한 원격 캐쉬 교체정책의 사용으로 상위 캐쉬의 유용한 캐쉬 라인의 접근 실패율을 감소시킴으로써 다중 프로세서 시스템의 성능 향상을 꾀한다. 프로그램 기반 시뮬레이터를 통해 제안한 원격 캐쉬 교체 정책을 적용하였을 때, 기존의 LRU 교체 정책과 비교하여 무효화 수와 캐쉬 접근 실패가 평균 5%. 최대 10% 감소하였다.

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A Main Memory-resident Multi-dimensional Index Structure Employing Partial-key and Compression Schemes (부분키 기법과 압축 기법을 혼용한 주기억장치 상주형 다차원 색인 구조)

  • 심정민;민영수;송석일;유재수
    • Journal of KIISE:Databases
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    • v.31 no.4
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    • pp.384-394
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    • 2004
  • Recently, to relieve the performance degradation caused by the bottleneck between CPU and main memory, cache conscious multi-dimensional index structures have been proposed. The ultimate goal of them is to reduce the space for entries so as to widen index trees and minimize the number of cache misses. The existing index structures can be classified into two approaches according to their entry reduction methods. One approach is to compress MBR keys by quantizing coordinate values to the fixed number of bits. The other approach is to store only the sides of minimum bounding regions (MBRs) that are different from their parents partially. In this paper, we propose a new index structure that exploits the properties of the both techniques. Then, we investigate the existing multi-dimensional index structures for main memory database system through experiments under the various work loads. We perform various experiments to show that our approach outperforms others.

An Efficient MBR Compression Technique for Main Memory Multi-dimensional Indexes (메인 메모리 다차원 인덱스를 위한 효율적인 MBR 압축 기법)

  • Kim, Joung-Joon;Kang, Hong-Koo;Kim, Dong-Oh;Han, Ki-Joon
    • Journal of Korea Spatial Information System Society
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    • v.9 no.2
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    • pp.13-23
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    • 2007
  • Recently there is growing Interest in LBS(Location Based Service) requiring real-time services and the spatial main memory DBMS for efficient Telematics services. In order to optimize existing disk-based multi-dimensional Indexes of the spatial main memory DBMS in the main memory, multi-dimensional index structures have been proposed, which minimize failures in cache access by reducing the entry size. However, because the reduction of entry size requires compression based on the MBR of the parent node or the removal of redundant MBR, the cost of MBR reconstruction increases in index update and the efficiency of search is lowered in index search. Thus, to reduce the cost of MBR reconstruction, this paper proposed the RSMBR(Relative-Sized MBR) compression technique, which applies the base point of compression differently in case of broad distribution and narrow distribution. In case of broad distribution, compression is made based on the left-bottom point of the extended MBR of the parent node, and in case of narrow distribution, the whole MBR is divided into cells of the same size and compression is made based on the left-bottom point of each cell. In addition, MBR was compressed using a relative coordinate and size to reduce the cost of search in index search. Lastly, we evaluated the performance of the proposed RSMBR compression technique using real data, and proved its superiority.

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Research on Event Mechanism for Reducing Power Overheads in Cache Memory Synchronization (캐시 메모리 동기화 전력 감소를 위한 이벤트 메커니즘에 대한 연구)

  • Pak, Young-Jin;Jeong, Ha-Young;Lee, Yong-Surk
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.48 no.3
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    • pp.69-75
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    • 2011
  • In this paper, we propose an anycast event driven synchronization mechanism to reduce power overheads. Our proposed mechanism can reduce unnecessary polling operations on SHI(Snoop Hit Invalidate) or SHR(Snoop Hit Read) states. It prevents waisting bandwidth and reduces power overheads on polling operation. Also it decreases transition power of state change compared to broadcast model. Simulation results indicated that the proposed architecture had about 15.3% of power decrease compared to spin-lock model and about 4.7% of power decrease compared to broadcast model. Overall results indicated that proposed synchronization mechanism could increase power efficiency of multi-core system by reducing power overheads.

Implementation and Performance Analysis of Efficient Packet Processing Method For DPI (Deep Packet Inspection) System using Dual-Processors (듀얼 프로세서 기반 DPI (Deep Packet Inspection) 엔진을 위한 효율적 패킷 프로세싱 방안 구현 및 성능 분석)

  • Yang, Joon-Ho;Han, Seung-Jae
    • The KIPS Transactions:PartC
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    • v.16C no.4
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    • pp.417-422
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    • 2009
  • Implementation of DPI(Deep Packet Inspection) system on a general purpose multiprocessor platform is an attractive option from the implementation cost point of view, since it does not require high-cost customized hardware. Load balancing has been considered as a primary means to achieve high performance in multi processor systems. We claim, however, that in case of DPI system design simply balancing the load of each processor does not necessarily yield the highest system performance. Instead, we propose a method in which tasks are allocated to processors based on their functions. We implemented the proposed method in dual processor Linux system and compare its performance with the existing load balancing methods. Under the proposed method, one processor is dedicated to deal with interrupt handling and generic packet processing, while another processor is dedicated to DPI processing. According to experimental results, the proposed scheme outperforms the existing schemes by 60%, mainly because of the reduction of cache miss and spin lock occurrences.

Data Communication Prediction Model in Multiprocessors based on Robust Estimation (로버스트 추정을 이용한 다중 프로세서에서의 데이터 통신 예측 모델)

  • Jun Janghwan;Lee Kangwoo
    • The KIPS Transactions:PartA
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    • v.12A no.3
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    • pp.243-252
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    • 2005
  • This paper introduces a noble modeling technique to build data communication prediction models in multiprocessors, using Least-Squares and Robust Estimation methods. A set of sample communication rates are collected by using a few small input data sets into workload programs. By applying estimation methods to these samples, we can build analytic models that precisely estimate communication rates for huge input data sets. The primary advantage is that, since the models depend only on data set size not on the specifications of target systems or workloads, they can be utilized to various systems and applications. In addition, the fact that the algorithmic behavioral characteristics of workloads are reflected into the models entitles them to model diverse other performance metrics. In this paper, we built models for cache miss rates which are the main causes of data communication in shared memory multiprocessor systems. The results present excellent prediction error rates; below $1\%$ for five cases out of 12, and about $3\%$ for the rest cases.

An Efficient Spatial Index Structure for Main Memory (메인 메모리를 위한 효율적인 공간 인덱스 구조)

  • Lee, Ki-Young;Lim, Myung-Jae;Kang, Jeong-Jin;Kim, Joung-Joon
    • The Journal of The Institute of Internet, Broadcasting and Communication
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    • v.9 no.2
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    • pp.13-20
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    • 2009
  • Recently there is growing interest in LBS requiring real-time services and the spatial main memory DBMS for efficient Telematics services. In order to optimize existing disk-based spatial indexes of the spatial main memory DBMS in the main memory, spatial index structures have been proposed, which minimize failures in cache access by reducing the entry size. However, because the reduction of entry size requires compression based on the MBR of the parent node or the removal of redundant MBR, the cost of MBR reconstruction increases in index update and the efficiency of search is lowered in index search. Thus, to reduce the cost of MBR reconstruction, this paper proposed the RSMB (relative-sized MBR)compression technique, which applies the base point of compression differently in case of broad distribution and narrow distribution. In case of broad distribution, compression is made based on the left-bottom point of the extended MBR of the parent node, and in case of narrow distribution, the whole MBR is divided into cells of the same size and compression is made based on the left-bottom point of each cell. In addition, MBR was compressed using a relative coordinate and size to reduce the cost of search in index search. Lastly, we evaluated the performance of the proposed RSMBR compression technique using real data, and proved its superiority.

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