• Title, Summary, Keyword: 클럭 카운터

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Design Technique of Register-based Asynchronous FIFO (레지스터 기반 비동기 FIFO 구조 설계 기법)

  • Lee, Yong-Hwan
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • v.9 no.1
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    • pp.1038-1041
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    • 2005
  • In today's SoC design, most of IPs which use the different clock frequency from that of the bus require asynchronous FIFOs. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, a register-based asynchronous FIFO is designed to transfer data in asynchronous clock domains by using a valid bits scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the gate level to compare with other FIFO scheme.

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Design of a Time-to-Digital Converter without Delay Time (지연시간 없는 시간-디지털 신호 변환기의 설계)

  • Choe, Jin-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.5
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    • pp.323-328
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    • 2001
  • A new time-to-digital converter is proposed which is based on a capacitor and a counter. The conventional time-to-digital converter requires rather longer processing time than the input time interval to obtain an accurate digital output. The resolution of the converted digital output is constant independent on the input time interval. However this study proposes the circuit in which the converted digital output can be obtained without delay time, and both the input time interval and the resolution can be easily improved through controlling passive device parameters.

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Fault Diagnosis and Tolerance for Asynchronous Counters with Critical Races Caused by Total Ionizing Dose in Space (우주 방사능 누적에 의한 크리티컬 레이스가 존재하는 비동기 카운터를 위한 고장 탐지 및 극복)

  • Kwak, Seong-Woo;Yang, Jung-Min
    • Journal of Korean Institute of Intelligent Systems
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    • v.22 no.1
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    • pp.49-55
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    • 2012
  • Asynchronous counters, where the counter value is changed not by a synchronizing clock but by outer inputs, are used in various modern digital systems such as spaceborne electronics. In this paper, we propose a scheme of fault tolerance for asynchronous counters with critical races caused by total ionizing dose (TID) in space. As a typical design flaw of asynchronous digital circuits, critical races cause an asynchronous circuit to show non-deterministic behavior, i.e., the next stable state of a state transition is not a fixed value but may be any value of a state set. Using the corrective control scheme for asynchronous sequential machines, this paper provides an existence condition and design procedure for a state feedback controller that can invalidate the effect of critical races. We implement the proposed control system in VHDL code and conduct experiments to demonstrate that the proposed control system can overcome critical races.

OTP Authentication Protocol Using Stream Cipher with Clock-Counter (클럭 카운트를 이용한 스트림 암호의 OTP 인증 프로토콜)

  • Cho, Sang-Il;Lee, Hoon-Jae;Lee, Sang-Gon;Lim, Hyo-Taek
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.13 no.10
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    • pp.2113-2120
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    • 2009
  • User authentication has been one of the most important part of the network system. OTP(One-Time Password) has been developed and applied to the existing authentication system. OTP makes a different password and abrogates used password each time when user is authenticated by the server. Those systems prevent stolen-key-problems which is caused by using the same key every log-in trial. Yet, OTP still has vulnerabilities. In this paper, an advanced protocol which is using clock-count method to apply a stream cipher algorithm to OTP protocols and to solve problems of existing OTP protocols is proposed.

Design of CMOS Temperature Sensor Using Ring Oscillator (링발진기를 이용한 CMOS 온도센서 설계)

  • Choi, Jin-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.9
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    • pp.2081-2086
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    • 2015
  • The temperature sensor using ring oscillator is designed by 0.18㎛ CMOS process and the supply voltage is 1.5volts. The temperature sensor is designed by using temperature-independent and temperature-dependent ring oscillators and the output frequency of temperature-independent ring oscillator is constant with temperature and the output frequency of temperature-dependent ring oscillator decreases with increasing temperature. To convert the temperature to a digital value the output signal of temperature-independent ring oscillator is used for the clock signal and the output signal of temperature-dependent ring oscillator is used for the enable signal of counter. From HSPICE simulation results, the temperature error is less than form -0.7℃ to 1.0℃ when the operating temperature is varied from -20℃ to 70℃.

Design of an Asynchronous FIFO for SoC Designs Using a Valid Bit Scheme (SoC 설계를 위한 유효 비트 방식의 비동기 FIFO설계)

  • Lee Yong-hwan
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.8
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    • pp.1735-1740
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    • 2005
  • SoC design integrates many IPs that operate at different frequencies and the use of the different clock for each IP makes the design the most effective one. An asynchronous FIFO is required as a kind of a buffer to connect IPs that are asynchronous. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, an asynchronous FIFO is designed to transfer data across asynchronous clock domains by using a valid bit scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the Bate level to compare with other FIFO scheme. The subject mater of this paper is under patent pending.

Design of a Time-to-Digital Converter Using Counter (카운터를 사용하는 시간-디지털 변환기의 설계)

  • Choi, Jin-Ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.3
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    • pp.577-582
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    • 2016
  • The synchronous TDC(Time-to-Digital Converter) of counter-type using current-conveyor is designed by $0.18{\mu}m$ CMOS process and the supply voltage is 3 volts. In order to compensate the disadvantage of a asynchronous TDC the clock is generated when the start signal is applied and the clock is synchronized with the start signal. In the asynchronous TDC the error range of digital output is from $-T_{CK}$ to $T_{CK}$. But the error range of digital output is from 0 to $T_{CK}$ in the synchronous TDC. The error range of output is reduced by the synchronization between the start signal and the clock when the timing-interval signal is converted to digital value. Also the structure of the synchronous TDC is simple because there is no the high frequency external clock. The operation of designed TDC is confirmed by the HSPICE simulation.

A study on the computer-controlled measuring device of complex dielectric constant (복소유전률 측정장치의 연구개발(컴퓨터제어 복소유전률 측정장치))

  • 남징락;엄상오;강대하
    • Electrical & Electronic Materials
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    • v.6 no.6
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    • pp.554-563
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    • 1993
  • 본 연구는 복소유전률 측정장치의 실현을 목표로 한 것이다. 본 장치는 인터페이스 유니트, 외부 RAM, 프로그래머블 카운터, D/A 콘버터, 측정회로, S&H 회로, A/D콘버터 및 기타 제어회로로 구성하였다. 컴퓨터에 의해 여러 종류의 파형이 디지털화하여 생성되며 4096워드의 외부 스태틱 RAM에 전송된다. 이와같이 RAM에 저장된 데이타는 D/A콘버터에 의하여 아날로그 전압파형으로 변환된다. 이 전압파형의 주파수는 클럭펄스에 의한 RAM의 읽기 속도에 좌우된다. 이와같이 생성된 전압파형이 유전체에 인가되며 이 인가전압과 함께 유전체의 응답전압이 샘플링되어 A/D콘버터에 의해 디지털 데이터로 변환된다. 컴퓨터는 응답전압 및 인가전압을 취하게 되며 마지막으로 복소유전률을 계산한다. 본 측정장치의 측정주파수 범위는 0.04Hz-10kHz이다.

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Variable Sampling Window Flip-Flops for High-Speed Low-Power VLSI (고속 저전력 VLSI를 위한 가변 샘플링 윈도우 플립-플롭의 설계)

  • Shin Sang-Dae;Kong Bai-Sun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.8
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    • pp.35-42
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    • 2005
  • This paper describes novel flip-flops with improved robustness and reduced power consumption. Variable sampling window flip-flop (VSWFF) adjusts the width of the sampling window according to input data, providing robust data latching as well as shorter hold time. The flip-flop also reduces power consumption for higher input switching activities as compared to the conventional low-power flip-flop. Clock swing-reduced variable sampling window flip-flop (CSR-VSWFF) reduces clock power consumption by allowing the use of a small swing clock. Unlike conventional reduced clock swing flip-flops, it requires no additional voltage higher than the supply voltage, eliminating design overhead related to the generation and distribution of this voltage. Simulation results indicate that the proposed flip-flops provide uniform latency for narrower sampling window and improved power-delay product as compared to conventional flip-flops. To evaluate the performance of the proposed flip-flops, test structures were designed and implemented in a $0.3\mu m$ CMOS process technology. Experimental result indicates that VSWFF yields power reduction for the maximum input switching activity, and a synchronous counter designed with CSR-VSWFF improves performance in terms of power consumption with no use of extra voltage higher than the supply voltage.

A Design of 16-bit Adiabatic Low-Power Microprocessor (단열회로를 이용한 16-bit 저전력 마이크로프로세서의 설계)

  • Shin, Young-Joon;Lee, Byung-Hoon;Lee, Chan-Ho;Moon, Yong
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.40 no.6
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    • pp.31-38
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    • 2003
  • A 16-bit adiabatic low-power Microprocessor is designed. The processor consists of control block, multi-port register file, program counter, and ALU. An efficient four-phase clock generator is also designed to provide power clocks for adiabatic processor. Adiabatic circuits based on efficient charge recovery logic(ECRL), are designed 0.35,${\mu}{\textrm}{m}$ CMOS technology. Conventional CMOS processor is also designed to compare the energy consumption of microprocessors. Simulation results show that the power consumption of the adiabatic microprocessor is reduced by a factor of 2.9∼3.1 compared to that of conventional CMOS microprocessor.