• Title, Summary, Keyword: A/D Converter

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An 8-bit 40 Ms/s Folding A/D Converter for Set-top box (Set-top box용 an 8-bit 40MS/s Folding A/D Converter의 설계)

  • Jang, Jin-Hyuk;Lee, Ju-Sang;Yu, Sang-Dae
    • Proceedings of the KIEE Conference
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    • pp.626-628
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    • 2004
  • This paper describes an 8-bit CMOS folding A/D converter for set-top box. Modular low-power, high-speed CMOS A/D converter for embedded systems aims at design techniques for low-power, high-speed A/D converter processed by the standard CMOS technology. The time-interleaved A/D converter or flash A/D converter are not suitable for the low-power applications. The two-step or multi-step flash A/D converters need a high-speed SHA, which represents a tough task in high-speed analog circuit design. On the other hand, the folding A/D converter is suitable for the low-power, high-speed applications(Embedded system). The simulation results illustrate a conversion rate of 40MSamples/s and a Power dissipation of 80mW(only analog block) at 2.5V supply voltage.

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Algorithm of Modified Single-slope A/D Converter with Improved Conversion Time for CMOS Image Sensor System

  • Lee, Sang-Hoon;Kim, Jin-Tae;Shin, Jang-Kyoo;Choi, Pyung
    • Journal of Sensor Science and Technology
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    • v.24 no.6
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    • pp.359-363
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    • 2015
  • This paper proposes an algorithm that reduces the conversion time of a single-slope A/D converter (SSADC) that has n-bit resolution, which typically is limited by conversion time taking up to $2^n$ clock cycles for an operation. To improve this situation, we have researched a novel hybrid-type A/D converter that consists of a pseudo-pipeline A/D converter and a conventional SSADC. The pseudo-pipeline A/D converter, using a single-stage of analog components, determines the most significant bits (MSBs) or upper bits and the conventional SSADC determines the remaining bits. Therefore, the modified SSADC, similar to the hybrid-type A/D converter, is able to significantly reduce the conversion time because the pseudo-pipeline A/D converter, which determines the MSBs (or upper bits), does not rely on a clock. The proposed A/D converter was designed using a $0.35-{\mu}m$ 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) technology process; additionally, its characteristics were simulated.

Sigma-Delta A/D Converter for ADSL Modems (ADSL 모뎀용 시그마-델타 아날로그/디지털 변환기)

  • Han, Seung-Yub;Yu, Sang-Dae;Lee, Ju-Sang
    • Proceedings of the KIEE Conference
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    • pp.950-953
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    • 2003
  • In this paper, sigma-delta A/D converter for ADSL modems using oversampling technique is designed. Conventionally, the oversampling A/D converter is consist of opamps, switched capacitors, quantizers, infernal D/A converters, and decimation filters. 3-bit flash A/D converter, 3-bit thermometer-based D/A converters, and sub-blocks are used for high speed operation. HSPICE simulator and CADENCE tool are used for verification and layout of the designed modulator. The internal A/D converter and D/A converters are operated at 130 MHz. In design of decimation filter Matlab is used for calculating coefficients and ModelSim and VHDL are used for design.

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Design of a TIQ Based CMOS A/D Converter for Real Time DSP (실시간 디지털 신호처리를 위한 TIQ A/D 변환기 설계)

  • Kim, Jong-Soo
    • Journal of the Institute of Convergence Signal Processing
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    • v.8 no.3
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    • pp.205-210
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    • 2007
  • This paper presents a CMOS TIQ flash A/D converter which operates very fast compared to other types of A/D converters due to its parallel architecture. The output resolution of designed A/D converter is 6-bit. In order to reduce the power consumption and chip area of conventional flash A/D converter, TIQ based flash A/D converter is proposed, which uses the advantage of the structure of CMOS transistors. The length and width of transistors of TIQ were determined with HSPICE simulation. To speed up the ultra-high speed flash A/D converter, the Fat Tree Encoder technique is used. The TIQ A/D converter was designed with full custom method. The chip's maximum power consumption was 38.45mW at 1.8V, and the operating speed of simulation was 2.7 GSPS.

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Design of a Low Power 10bit Flash SAR A/D Converter (저 전력 10비트 플래시-SAR A/D 변환기 설계)

  • Lee, Gi-Yoon;Kim, Jeong-Heum;Yoon, Kwang-Sub
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.40 no.4
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    • pp.613-618
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    • 2015
  • This paper proposed a low power CMOS Flash-SAR A/D converter which consists of a Flash A/D converter for 2 most significant bits and a SAR A/D converter with capacitor D/A converter for 8 least significant bits. Employment of a Flash A/D converter allows the proposed circuit to enhance the conversion speed. The SAR A/D converter with capacitor D/A converter provides a low power dissipation. The proposed A/D converter consumes $136{\mu}W$ with a power supply of 1V under a $0.18{\mu}m$ CMOS process and achieves 9.16 effective number of bits for sampling frequency up to 2MHz. Therefore it results in 120fJ/step of Figure of Merit (FoM).

A 3.3V 8-bit 500MSPS Nyquist CMOS A/D Converter Based on an Interpolation Architecture (Interpolation 기법을 이용한 3.3V 8-bit 500MSPS Nyquist CMOS A/D Converter의 설계)

  • 김상규;송민규
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.8
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    • pp.67-74
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    • 2004
  • In this paper, a 3.3V 8-bit 500MSPS based on an interpolation architecture CMOS A/D converter is designed. In order to overcome the problems of high speed operation, a novel pre-amplifier, a circuit for the Reference Fluctuation, and an Averaging Resistor are proposed. The proposed Interpolation A/D Converter consists of Track & Hold, four resistive ladders with 256 taps, 128 comparators, and digital blocks. The proposed A/D Converter is based on 0.35um 2-poly 4-metal N-well CMOS technology. The A/D Converter dissipates 440 mW at a 3.3 Volt single power supply and occupies a chip area of 2250um x 3080um.

Circuit design of current driving A/D converter (전류 구동형 A/D converter 회로 설계)

  • Lee, Jong-Gyu;Oh, Woo-Jin;Kim, Myung-Sik
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.11
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    • pp.2100-2106
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    • 2007
  • Multi-stage folding A/D converter circuit with $0.25{\mu}m$ N-well CMOS technology is designed. This A/D converter consists of a transconductance circuit, linear folder circuit and 1bit A/D converter circuit. In H-spice simulation results, linear folder circuits having high linearity can be obtained when the current mode is used instead of voltage mode. And in case of 6bit, the delay time is limited about 40ns. From this results, 6bit 25MSPS A/D converter circuit can be realized.

Digital Current Control Scheme for Boost Single-Phase PFC Converter Based on Virtual d-q Transformation (가상 d-q 변환을 이용한 승압형 단상 PFC 컨버터의 디지털 전류 제어 방법)

  • Lee, Kwang-Woon;Kim, Hack-Jun
    • The Transactions of the Korean Institute of Power Electronics
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    • v.25 no.1
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    • pp.54-60
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    • 2020
  • A digital current control scheme using virtual d-q transformation for a boost single-phase power factor correction (PFC) converter is proposed. The use of virtual d-q transformation in single-phase power converters is known to improve current control performance. However, the conventional virtual d-q transformation-based digital current control scheme cannot be directly applied to the boost single-phase PFC converter because the current and average voltage waveforms of the inductor used in the converter are not sinusoidal. To cope with this problem, this study proposes a virtual sinusoidal signal generation method that converts the current and average voltage waveform of the inductor into a sinusoidal waveform synchronized with the grid. Simulation and experimental results are provided to show that the virtual d-q transformation-based digital current control is successfully applied to the boost single-phase PFC converter with the aid of the proposed virtual sinusoidal signal generation method.

Effect of L.D Converter Slag Hardener on the Collapsibility of Sand Molds Using Sodium Silicate Binder (규산소오다계 자경성주형의 붕괴성에 미치는 L.D 전로 슬래그 경화제의 영향)

  • Choi, Jun-Oh;Park, Sung-Taik;Han, Yun-Sung;Choi, Chang-Ock
    • Journal of Korea Foundry Society
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    • v.23 no.5
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    • pp.235-243
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    • 2003
  • The collapsibility of sodium silicate-bonded sands mixed with the L.D converter slag powder to form a hardener were investigated. Five to six percent sodium silicate on the basis of silica sand and 30-40% L.D converter slag powder on the basis of sodium silicate, were mixed and the compressive strength, surface stability index(SSI), bench time, retained strength of the standard sand specimens were measured. The properties were similar to those of general inorganic bonded self-setting molds. The compressive strength and surface stability index were increased and the retained strength and bench time were decreased with increased amount of the L.D converter slag powder. The retained strength of sodium silicate-bonded self-setting molds with the L.D converter slag powder were decreased than $CO_2$ sand molds. The collapsibility of sodium silicate-bonded self-setting molds with the L.D converter slag powder were superior in comparison with $CO_2$ sand molds. The L.D converter slag powder could be used as hardener and collapse agent for the sodium silicate-bonded self-setting molds.

Test Algorithm and Measurement of Housekeeping A/D Converter (하우스킵핑 A/D 변환기의 테스트 알고리즘과 측정)

  • 박용수;유흥균
    • Journal of the Semiconductor & Display Technology
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    • v.3 no.4
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    • pp.19-27
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    • 2004
  • The characteristic evaluation of A/D converter is to measure the linearity of the converter. The evaluation of the linearity is to measure the DNL, INL, gain error and offset error in the various test parameters of A/D converter. Generally, DNL and INL are to be measured by the Histogram Test Algorithm in the DSP-based ATE environment. And gain error and offset error are to be measured by the calculation equation of the measuring algorithm. It is to propose the new Concurrent Histogram Test Algorithm for the test of the housekeeping A/D converter used in the CDMA cellular phone. Using the proposed method, it is to measure the DNL, INL, gain error and offset error concurrently and to show the measured results.

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