• Title, Summary, Keyword: Address translation

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Wireless Internet Broadcasting System for LBS (LBS를 위한 무선인터넷 지역방송 시스템)

  • Oh, Jong-Taek;Lee, Bong-Gyou
    • Journal of Korea Spatial Information System Society
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    • v.5 no.1
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    • pp.75-81
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    • 2003
  • In spite of widely deploying information broadcasting services based on Internet, there are some limitations to use them due to the bound of Internet protocol. In this paper, a new Internet broadcasting technology for access network and Location Based Services are proposed by employing IP address translation function in base station. There are some advantages such as, no need to allocate IP address to receiver no need to know web site address, and reduction of traffic for server and network.

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Peducing the Overhead of Virtual Address Translation Process (가상주소 변환 과정에 대한 부담의 줄임)

  • U, Jong-Jeong
    • The Transactions of the Korea Information Processing Society
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    • v.3 no.1
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    • pp.118-126
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    • 1996
  • Memory hierarchy is a useful mechanism for improving the memory access speed and making the program space larger by layering the memories and separating program spaces from memory spaces. However, it needs at least two memory accesses for each data reference : a TLB(Translation Lookaside Buffer) access for the address translation and a data cache access for the desired data. If the cache size increases to the multiplication of page size and the cache associativity, it is difficult to access the TLB with the cache in parallel, thereby making longer the critical timing path in the processor. To achieve such parallel accesses, we present the hybrid mapped TLB which combines a direct mapped TLB with a very small fully-associative mapped TLB. The former can reduce the TLB access time. while the latter removes the conflict misses from the former. The trace-driven simulation shows that under given workloads the proposed TLB is effective even when a fully-associative mapped TLB with only four entries is added because the effects of its increased misses are offset by its speed benefits.

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An Address Translation Technique Large NAND Flash Memory using Page Level Mapping (페이지 단위 매핑 기반 대용량 NAND플래시를 위한 주소변환기법)

  • Seo, Hyun-Min;Kwon, Oh-Hoon;Park, Jun-Seok;Koh, Kern
    • Journal of KIISE:Computing Practices and Letters
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    • v.16 no.3
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    • pp.371-375
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    • 2010
  • SSD is a storage medium based on NAND Flash memory. Because of its short latency, low power consumption, and resistance to shock, it's not only used in PC but also in server computers. Most SSDs use FTL to overcome the erase-before-overwrite characteristic of NAND flash. There are several types of FTL, but page mapped FTL shows better performance than others. But its usefulness is limited because of its large memory footprint for the mapping table. For example, 64MB memory space is required only for the mapping table for a 64GB MLC SSD. In this paper, we propose a novel caching scheme for the mapping table. By using the mapping-table-meta-data we construct a fully associative cache, and translate the address within O(1) time. The simulation results show more than 80 hit ratio with 32KB cache and 90% with 512KB cache. The overall memory footprint was only 1.9% of 64MB. The time overhead of cache miss was measured lower than 2% for most workload.

A Mapping Table Caching Scheme for NAND Flash-based Mobile Storage Devices (NAND 플래시 기반 모바일 저장장치를 위한 사상 테이블 캐싱 기법)

  • Yang, Soo-Hyeon;Ryu, Yeon-Seung
    • The Journal of Society for e-Business Studies
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    • v.15 no.4
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    • pp.21-31
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    • 2010
  • Recently e-business such as online financial trade and online shopping using mobile computes are widely spread. Most of mobile computers use NAND flash memory-based storage devices for storing data. Flash memory storage devices use a software called flash translation layer to translate logical address from a file system to physical address of flash memory by using mapping tables. The legacy FTLs have a problem that they must maintain very large mapping tables in the RAM. In order to address this issues, in this paper, we proposed a new caching scheme of mapping tables. We showed through the trace-driven simulations that the proposed caching scheme reduces the space overhead dramatically but does not increase the time overhead. In the case of online transaction workload in e-business environment, in particular, the proposed scheme manifests better performance in reducing the space overhead.

A Snoop-Based Kernel Introspection System against Address Translation Redirection Attack (메모리 주소 변환 공격을 탐지하기 위한 Snoop기반의 커널 검사 시스템)

  • Kim, Donguk;Kim, Jihoon;Park, Jinbum;Kim, Jinmok
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.26 no.5
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    • pp.1151-1160
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    • 2016
  • A TrustZone-based rootkit detecting solution using a secure timer ensures the integrity of monitoring system, because ARM TrustZone technology provides isolated environments from a monitored OS against intercepting and modifying invoke commands. However, it is vulnerable to transient attack due to periodic monitoring. Also, Address Translation Redirection Attack (ATRA) cannot be detected, because the monitoring is operated by using the physical address of memory. To ameliorate this problem, we propose a snoop-based kernel introspection system. The proposed system can monitor a kernel memory in real-time by using a snooper, and detect memory-bound ATRA by introspecting kernel pages every context switch of processes. Experimental results show that the proposed system successfully protects the kernel memory without incurring any significant performance penalty in run-time.

AS B-tree: A study on the enhancement of the insertion performance of B-tree on SSD (AS B-트리: SSD를 사용한 B-트리에서 삽입 성능 향상에 관한 연구)

  • Kim, Sung-Ho;Roh, Hong-Chan;Lee, Dae-Wook;Park, Sang-Hyun
    • The KIPS Transactions:PartD
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    • v.18D no.3
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    • pp.157-168
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    • 2011
  • Recently flash memory has been being utilized as a main storage device in mobile devices, and flashSSDs are getting popularity as a major storage device in laptop and desktop computers, and even in enterprise-level server machines. Unlike HDDs, on flash memory, the overwrite operation is not able to be performed unless it is preceded by the erase operation to the same block. To address this, FTL(Flash memory Translation Layer) is employed on flash memory. Even though the modified data block is overwritten to the same logical address, FTL writes the updated data block to the different physical address from the previous one, mapping the logical address to the new physical address. This enables flash memory to avoid the high block-erase cost. A flashSSD has an array of NAND flash memory packages so it can access one or more flash memory packages in parallel at once. To take advantage of the internal parallelism of flashSSDs, it is beneficial for DBMSs to request I/O operations on sequential logical addresses. However, the B-tree structure, which is a representative index scheme of current relational DBMSs, produces excessive I/O operations in random order when its node structures are updated. Therefore, the original b-tree is not favorable to SSD. In this paper, we propose AS(Always Sequential) B-tree that writes the updated node contiguously to the previously written node in the logical address for every update operation. In the experiments, AS B-tree enhanced 21% of B-tree's insertion performance.

AFTL: An Efficient Adaptive Flash Translation Layer using Hot Data Identifier for NAND Flash Memory (AFTL: Hot Data 검출기를 이용한 적응형 플래시 전환 계층)

  • Yun, Hyun-Sik;Joo, Young-Do;Lee, Dong-Ho
    • Journal of KIISE:Computer Systems and Theory
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    • v.35 no.1
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    • pp.18-29
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    • 2008
  • NAND Flash memory has been growing popular storage device for the last years because of its low power consumption, fast access speed, shock resistance and light weight properties. However, it has the distinct characteristics such as erase-before-write architecture, asymmetric read/write/erase speed, and the limitation on the number of erasure per block. Due to these limitations, various Flash Translation Layers (FTLs) have been proposed to effectively use NAND flash memory. The systems that adopted the conventional FTL may result in severe performance degradation by the hot data which are frequently requested data for overwrite in the same logical address. In this paper, we propose a novel FTL algorithm called Adaptive Flash Translation Layer (AFTL) which uses sector mapping method for hot data and log-based block mapping method for cold data. Our system removes the redundant write operations and the erase operations by the separating hot data from cold data. Moreover, the read performance is enhanced according to sector translation that tends to use a few read operations. A series of experiments was organized to inspect the performance of the proposed method, and they show very impressive results.

Implementation of Static Address-Internetworking Scheme between Wireless Sensor Network and Internet (센서 네트워크와 인터넷과의 정적 주소 연동 방안 구현)

  • Kim, Jeong-Hee;Kwon, Hoon;Kwak, Ho-Young;Do, Yang-Hoi;Byun, Yung-Cheol;Kim, Do-Hyeun
    • The Journal of the Korea Contents Association
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    • v.6 no.12
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    • pp.40-49
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    • 2006
  • As a promising integrated circuit, wireless communication and micro-computing technology, the technology of sensor network that will lead the information technology industries of the next generation and realize the ubiquitous computing is one of the most active research topics and its research activities are also making today. From now on, each node, the network formation, and even the sensor network itself will interact with the generic network and evolve dynamically according to environmental changes in a process of continual creation and extinction. Therefore, address-internetworking between sensor network and generic network which are used different address mechanism is required. In this paper, we propose a static address-internetworking scheme for interactive networking between a sensor network and the Internet. The proposed scheme that possess a gateway approach to perform the protocol translation from one protocol to another, an overlay approach to constructs an overlay network on the WSNs and enables static internetworking between a sensor network address scheme based on Zigbee and the Internet address scheme based on the Internet Protocol. In addition, we verify the proposed scheme by an interconnection experiment.

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A study on congesting control scheme for LAN interworkding in connectionless data service (비연결형 데이터 서비스에서 LAN연동을 위한 폭주 제어에 관한 연구)

  • 박천관;전병천;김영선
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.35S no.3
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    • pp.29-38
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    • 1998
  • This ppaer suggests a congestion control scheme for CL(ConnectionLess) overlay network using the feedback loops getween CL werver, between CL servers, and the header translation table of CL server. The CL overlay network for CBDS(Connectionless Broadband Data Service) defined by ITU0T(International Telecommunication Union-Telecommunication) consists of CL servers which route frames and links which connect between CL user and CL server or between CL servers. In this CL overlay network, two kinds of congestions, link congestion and CL server congestion, may occur. We suggest a scheme that can solve the congestion using ABR(Available Bit Rate) feedback control loop, the traffic control mechanism. This scheme is the link-by-link method suing the ABR feedback control loops between CL user and CL server or between CL servers, and the header translation table of CL server. As CL servers are always endpoints of ABR connections, the congestion staturs of the CL server can be informed to the traffic sources using RM(Resource Management) cell of the ABR feedback loops. Also CL server knows the trafffic sources making congestion by inspecting the source address field of CLNAP-PDUs(ConnectionLess Network Access Protocol - Protocol Data Units). Therefore this scheme can be implemeted easily using only both ABR feedback control loop of ATM layer and the congestion state table using the header translation table of CL server because it does not require separate feedback links for congestion control of CL servers.

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Improvement Method for IPv4/IPv6 Transformation using Multiple NAT-PT (다중 NAT-PT를 이용한 IPv4/IPv6 변환 개선방법)

  • 최원순;노희영
    • Proceedings of the Korean Information Science Society Conference
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    • pp.811-813
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    • 2004
  • IPv6는 IPv4 기반의 인터넷의 주소고갈과 새로운 부가 기능 등의 필요성 때문에 IETF에서 IPv4를 대체하기 위해 채택 된 프로토콜이다. 하지만 IPv4를 어느 한순간에 IPv6로 대체하는 것은 불가능하기 때문에 기존 IPv4와의 호환 및 연동을 위한 여러 메커니즘이 연구되었다. 그 중 NAT-PT(Network Address Translation-Protocol Translation)는 IPv4/IPv6 헤더 변환기술을 적용한 대표적인 변환 메커니즘이며, IP 패킷을 통과하는 망의 IP버전에 맞게 변환 시켜서 전송하는 방식이다. 그러나 모든 패킷들이 하나의 NAT-PT 노드로 집중되므로 병목현상이 발생하며, 이로 인해 성능저하가 발생한다. 본 논문은 NAT-PT 병목현상을 줄이기 위한 방안으로 DNS-ALG 기반된 서버를 이용하여 다중 NAT-PT를 사용한 방법을 제안한다.

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