• Title, Summary, Keyword: Bit 구조

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Replica Technique regarding research for Bit-Line tracking (비트라인 트래킹을 위한 replica 기술에 관한 연구)

  • Oh, Se-Hyeok;Jung, Han-wool;Jung, Seong-Ook
    • Journal of IKEEE
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    • v.20 no.2
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    • pp.167-170
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    • 2016
  • Replica bit-line technique is used for making enable signal of sense amplifier which accurately tracks bit-line of SRAM. However, threshold voltage variation in the replica bit-line circuit changes the cell current, which results in variation of the sense amplifier enable time, $T_{SAE}$. The variation of $T_{SAE}$ makes the sensing operation unstable. In this paper, in addition to conventional replica bit-line delay ($RBL_{conv}$), dual replica bit-line delay (DRBD) and multi-stage dual replica bit-line delay (MDRBD) which are used for reducing $T_{SAE}$ variation are briefly introduced, and the maximum possible number of on-cell which can satisfy $6{\sigma}$ sensing yield is determined through simulation at a supply voltage of 0.6V with 14nm FinFET technology. As a result, it is observed that performance of DRBD and MDRBD is improved 24.4% and 48.3% than $RBL_{conv}$ and energy consumption is reduced which 8% and 32.4% than $RBL_{conv}$.

Low Power Cryptographic Design based on Circuit Size Reduction (회로 크기 축소를 기반으로 하는 저 전력 암호 설계)

  • You, Young-Gap;Kim, Seung-Youl;Kim, Yong-Dae;Park, Jin-Sub
    • The Journal of the Korea Contents Association
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    • v.7 no.2
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    • pp.92-99
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    • 2007
  • This paper presented a low power design of a 32bit block cypher processor reduced from the original 128bit architecture. The primary purpose of this research is to evaluate physical implementation results rather than theoretical aspects. The data path and diffusion function of the processor were reduced to accommodate the smaller hardware size. As a running example demonstrating the design approach, we employed a modified ARIA algorithm having four S-boxes. The proposed 32bit ARIA processor comprises 13,893 gates which is 68.25% smaller than the original 128bit structure. The design was synthesized and verified based on the standard cell library of the MagnaChip's 0.35um CMOS Process. A transistor level power simulation shows that the power consumption of the proposed processor reduced to 61.4mW, which is 9.7% of the original 128bit design. The low power design of the block cypher Processor would be essential for improving security of battery-less wireless sensor networks or RFID.

A High Density Memory Device for Next Generation Low-Voltage and High-Speed Operations (차세대 저 전압, 고속 동작 요구에 대응하는 대용량 메모리의 개발)

  • 윤홍일;이현석;유형식;천기철
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • pp.3-5
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    • 2000
  • 1.8V,4Gb DDR SDRAM설계 및 제작을 수행하였다. DRAM동작 시 발생하는 Bit Line간 CouplingNoise를 보상하기 위한 Twisted Open Bit Line 구조를 제안하였다. Low Voltage Operation으로 인한 Bit Line Sense Amplifier 의 동작 저하를 보상하기 위한 BL S/A Pre-Sensing 방식 및 Reference Bit Line Voltage Calibration 구조를 제안하였다. Chip면적 증가로 인한 동작속도 감소의 보상을 위해 Repeater Driver 구조를 Core 및 Periphery Circuit에 적용하여 동작 대비 Chip 면적의 증가를 최소화 하도록 하였다.

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Complexity Analysis of a VHDL Implementation of the Bit-Serial Reed-Solomon Encoder (VHDL로 구현된 직렬승산 리드솔로몬 부호화기의 복잡도 분석)

  • Back Seung hun;Song Iick ho;Bae Jin soo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.3C
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    • pp.64-68
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    • 2005
  • Reed-Solomon code is one of the most versatile channel codes. The encoder can be implemented with two famous structures: ordinary and bit-serial. The ordinary encoder is generally known to be complex and fast, while the bit-serial encoder is simple and not so fast. However, it may not be true for a longer codeword length at least in VHDL implementation. In this letter, it is shown that, when the encoder is implemented with VHDL, the number of logic gates of the bit-serial encoder might be larger than that of the ordinary encoder if the dual basis conversion table has to be used. It is also shown that the encoding speeds of the two VHDL implemented encoders are exactly same.

Video Content-Based Bit Rate Estimation (비디오 콘텐츠 기반 비트율 예측)

  • Huang, Fei;Lee, Jaeyong;Oh, Seoung-Jun
    • Journal of Broadcast Engineering
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    • v.18 no.2
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    • pp.297-310
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    • 2013
  • In this paper, we present a model-based video bit rate estimation scheme for reducing the bit rate while maintaining a subjective quality in many video streaming services limited by network bandwidth, such as IPTV services. First, we extract major parameters which serve as an indirect measurement of frame's bits. Using those parameters, the proposed bit rate estimation scheme can extract candidate frames. Finally, the bit rate of each segment is estimated by statistical analysis and a mathematical model based on a given target quality. In experimental results, we show that the proposed scheme can reduce the bit rate on average by 43% in low-complexity video while maintaining the subjective quality. To find the appropriate bit rate based on video contents, the proposed schemes can estimate the bit rate with neither the repeated full encoding nor subjective quality test. On average, the bit rate can be automatically estimated by encoding the candidate frames of 4%.

A new bit line structure minimizing coupling noise for DRAM (DRAM의 비트 라인 간 커플링 노이즈를 최소화한 오픈 비트 라인구조)

  • Oh, Myung-Kyu;Jo, Kyoung-Rok;Kim, Sung-Sik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.6
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    • pp.17-24
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    • 2004
  • This paper describes a novel bit line structure to minimize coupling noise induced by coupling capacitance between bit lines. In DRAMs coupling capacitance is inherently present bit lines. As in submicron process the bit line space gets narrower. bit line coupling capacitance increases and this increased coupling capacitance sharply raises cross-talk noise. In this paper using different layers of metal for adjacent bit lines has been tested to reduces cross-talk noise and a novel bit line structure capable of reducing capacitance is introduced and verified.

Design of Novel OTP Unit Bit and ROM Using Standard CMOS Gate Oxide Antifuse (표준 CMOS 게이트 산화막 안티퓨즈를 이용한 새로운 OTP 단위 비트와 ROM 설계)

  • Shin, Chang-Hee;Kwon, Oh-Kyong
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.5
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    • pp.9-14
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    • 2009
  • In this paper, we proposed a novel OTP unit bit of CMOS gate oxide antifuse using the standard CMOS process without additional process. The proposed OTP unit bit is composed of 3 transistors including an NMOS gate oxide antifuse and a sense amplifier of inverter type. The layout area of the proposed OTP unit bit is $22{\mu}m^2$ similar to a conventional OTP unit bit. The programming time of the proposed OTP unit bit is 3.6msec that is improved than that of the conventional OTP unit bit because it doesn't use high voltage blocking elements such as high voltage blocking switch transistor and resistor. And the OTP array with the proposed OTP unit bit doesn't need sense amplifier and bias generation circuit that are used in a conventional OTP array because sense amplifier of inverter type is included to the proposed OTP unit bit.

A 10-bit 1-MHz Cyclic A/D Converter with Time Interleaving Architecture and Digital Error Correction (시분할 구조와 디지털 에러 보상을 사용한 10비트 1MHz 사이클릭 아날로그-디지털 변환기)

  • 성준제;김수환
    • Proceedings of the IEEK Conference
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    • pp.715-718
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    • 1998
  • 본 논문에서는 시분할 구조와 1.5bit 디지털 에러보상을 사용하여 작은 면적을 갖는 저 전압, 저전력 10bit 1㎒ 사이클릭 A/D 변환기를 제안하였다. 제안된 사이클릭 A/D 변환기는 시분할 구조를 사용함으로서 변환속도의 향상과 저 전력 특성을 가질 수 있었으며 1.5bit 디지털 에러 보상을 사용함으로서 10bit의 고해상도와 저 전력 특성을 구현할 수 있었다. 제안된 사이클릭 A/D 변환기는 0.6㎛ CMOS Nwell 공정 parameter로 simulation 하였으며 layout 결과 칩면적은 1.1㎜×0.8㎜ 이며 이는 비슷한 성능을 갖는 다른 A/D 변환기에 비하여 매우 작은 크기이다. 제안된 사이클릭 A/D 변환기는 3V의 전원전압에 1.6㎽의 전력소모를 갖는다. Matlab simulation 결과 INL, DNL은 각각 0.6LSB, 0.7LSB 이하의 값을 보였다.

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Selective HAVE Message Exchange for the Improvement of Live Streaming Performance in BitTorrent-based Mesh-Pull Structure (BitTorrent 기반의 Mesh-Pull 구조에서 라이브 스트리밍 성능 개선을 위한 선택적인 HAVE 메시지 전송 방법)

  • Han, Ho-Dol;Kim, Seongmin;Roh, Byeong-hee
    • Proceedings of the Korea Information Processing Society Conference
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    • pp.310-313
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    • 2013
  • BitTorrent는 파일 공유를 위하여 가장 널리 사용되고 있는 P2P (Peer to Peer)프로토콜로서, Mesh-Pull 구조를 채용하여 라이브 스트리밍에 대한 연구가 꾸준히 이루어지고 있다. BitTorrent에서는 Peer Wire Protocol을 사용하여 피어들간에 파일조각들을 교환하게 되는데, 이를 위하여 주기적으로 버퍼맵 정보를 HAVE 메시지를 사용하여 브로드캐스트 하는데, 피어의 수가 증가할수록 이로 인한 시그널링 오버헤드가 크게 증가하는 문제를 갖고 있다. 본 논문에서는 이러한 문제를 극복하고 라이브 스트리밍의 성능을 개선하기 위하여 HAVE 메시지를 선택적으로 전송하는 방법을 제안한다. 실험을 통하여, 제안 방식은 기존의 BitTorrent 기반 Mesh-Pull 구조를 채용하는 라이브 스트리밍 방식과 비교하여 HAVE 메시지의 브로드캐스트로 인한 시그널링 오버헤드를 비약적으로 줄일 수 있음을 보였다.

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Design of Square Root and Inverse Square Root Arithmetic Units for Mobile 3D Graphic Processing (모바일 3차원 그래픽 연산을 위한 제곱근 및 역제곱근 연산기 구조 및 설계)

  • Lee, Chan-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.3
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    • pp.20-25
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    • 2009
  • We propose hardware architecture of floating-point square root and inverse square root arithmetic units using lookup tables. They are used for lighting engines and shader processor for 3D graphic processing. The architecture is based on Taylor series expansion and consists of lookup tables and correction units so that the size of look-up tables are reduced. It can be applied to 32 bit floating point formats of IEEE-754 and reduced 24 bit floating point formats. The square root and inverse square root arithmetic units for 32 bit and 24 bit floating format number are designed as the proposed architecture. They can operation in a single cycle, and satisfy the precision of $10^{-5}$ required by OpenGL 1.x ES. They are designed using Verilog-HDL and the RTL codes are verified using an FPGA.