• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2891-2902
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• 1997

This paper presents an analysis on the optimal partitioning configuration of cache (memory) for meeting deadlines of periodic and aperiodic real-time task set. Our goal is not only to decrease the deadline missing ratio of each task by minimizing the task utilization, but also to allocate another tasks to idle spaces of cache. For this reason, we suggest an algorithm so that tasks could be allocated to cache segments. Here, the set of cache segments allocated tasks is called a cache partitioning configuration. Based on how tasks allocate to cache segments, we can get various cache partitioning configurations. From these configurations, we obtain the boundary of task utilization that tasks are possible to schedule, and analyze the cache optimal partitioning configuration that can be executed to minimize the task utilization.

• Journal of the Korea Society for Simulation
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• v.12 no.2
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• pp.35-44
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• 2003

The effectiveness of buffer cache replacement algorithms is critical to the performance of I/O systems. In this paper, we propose the degree of inter-reference gap (DIG) based block replacement scheme that retains merits of the least recently used (LRU) such as simple implementation and good cache hit ratio (CHR) for general patterns of references, and improves CHR further. In the proposed scheme, cache blocks with low DIGs are distinguished from blocks with high DIGs and the replacement block is selected among high DIGs blocks as done in the low inter-reference recency set (LIRS) scheme. Thus, by having the effect of the partitioning the cache memory dynamically based on DIGs, CHR is improved. Trace-driven simulation is employed to verified the superiority of the DIG based scheme and shows that the performance improves up to about 175% compared to the LRU scheme and 3% compared to the LIRS scheme for the same traces.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.1
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• pp.43-54
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• 2010

The existing timeout based cache leakage management techniques reduce the leakage energy consumption of the cache significantly by switching off the power supply to the inactive cache line. Since these techniques were mainly proposed for single-processor systems, their efficiency is reduced significantly in multiprocessor systems with a shared L2 cache because of the cache interferences among simultaneously executing tasks. In this paper, we propose a novel cache partition strategy which partitions the shared L2 cache considering the inactive cycles of the cache line. Furthermore, we propose the adaptive task-aware timeout management technique which considers the characteristics of each task and adapts the timeout dynamically. Experimental results from the simulation show that the proposed technique reduces the leakage energy consumption of the shared L2 cache by 73% for the 2-way CMP and 56% for the 4-way CMP on average compared to the existing representative leakage management technique, respectively.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.5
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• pp.241-251
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• 2007

Energy consumption in the instruction cacheaccounts for a significant portion of the total processor energy consumption. Therefore, reducing energy consumption in the instruction cache is important in designing embedded processors. This paper proposes a method for reducing dynamic energy consumption in the instruction cache by partitioning it to smaller (less energy-consuming) sub-caches. When a request comes into the proposed cache, only one sub-cache is accessed by utilizing the locality of applications. By contrast, the other sub-caches are not accessed, leading todynamic energy reduction. In addition, the proposed cache reduces dynamic energy consumption by eliminating the energy consumed in tag matching. We evaluated the energy efficiency by running cycle accurate simulator, SimpleScalar. with power parameters obtained from CACTI. Simulation results show that the proposed cache reduces dynamic energy consumption by $37%{\sim}60%$ compared to the traditional direct-mapped instruction cache.

• IEMEK Journal of Embedded Systems and Applications
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• v.14 no.2
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• pp.71-78
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• 2019

As the capacity of SSDs rapidly increases, the amount of DRAM to keep a mapping table size in SSDs becomes very huge. To address a Demand-based FTL (DFTL) scheme that caches part of mapping entries in DRAM is considered to be a feasible alternative. However, owing to its unpredictable behaviors, DFTL fails to provide consistent I/O response times. In this paper, we a) analyze a root cause that results in fluctuation on read latency and b) propose a new demand-based FTL scheme that ensures guaranteed read response time with low write amplification. By preventing mapping evictions while serving reads, the proposed technique guarantees every host read requests to be done in 2 NAND read operations. Moreover, only with 25% of a cache ratio, the proposed scheme improves random write performance and random mixed performance by 1.65x and 1.15x, respectively, over the traditional DFTL.

• Journal of KIISE:Databases
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• v.34 no.4
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• pp.328-342
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• 2007

We propose a new cache conscious indexing structure for processing frequently updated data efficiently. Our proposed index structure is based on a KDB-Tree, one of the representative index structures based on space partitioning techniques. In this paper, we propose a data compression technique and a pointer elimination technique to increase the utilization of a cache line. To show our proposed index structure's superiority, we compare our index structure with variants of the CR-tree(e.g. the FF CR-tree and the SE CR-tree) in a variety of environments. As a result, our experimental results show that the proposed index structure achieves about 85%, 97%, and 86% performance improvements over the existing index structures in terms of insertion, update and cache-utilization, respectively.

• Proceedings of the Korean Information Science Society Conference
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• pp.346-348
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• 2000

전통적일 파일 캐쉬나 가상 메모리 시스템과 웹 캐쉬는 다르다. 웹 캐쉬는 WWW상에서 작게는 수백 바이트에서 크게는 수십 메가바이트에 이르는 다양한 크기의 개체를 다루어야 한다. 다양한 크기의 개체를 다루는데 따른 문제점은 캐쉬 성능을 판단하는 매트릭스가 단순한 hit rate가 아니라는 것이다. 기본적인 웹 캐쉬의 성능 매트릭스로는 HR(cache hit rate)와 BHR(byte cache hit rate)가 있으며, 기존에 제시된 캐쉬 정책들은 두 가지 중 하나만을 만족하거나 아니면 어느 것도 만족하지 않는 경우가 대부분이다. 트레이스 드리븐 방식을 이용한 시뮬레이션을 통하여, 기존에 우수성이 입증된 캐쉬 대체 정책과 우리가 제시한 TYPE 대체 정책을 HR과 BHR을 기준으로 비교한다. 우리가 제시한, 파일 타입에 대해 동적으로 할당된 캐쉬 공간을 갖는 캐쉬 대체기법은 각각의 두 성능 매트릭스에 대해서 골고루 우수한 성능을 보였다.

• Journal of the Korea Society of Computer and Information
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• v.18 no.11
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• pp.1-12
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• 2013

In multi-core processors, Last Level Cache(LLC) can reduce the speed gap between the memory and the core. For this reason, LLC has big impact on the performance of processors. LLC is composed of shared cache and private cache. In computer architecture community, most researchers have mainly focused on the management techniques for shared cache, while management techniques for private cache have not been widely researched. In conventional private LLC, memory is statically assigned to each core, resulting in serious performance degradation when the workloads are not fairly distributed. To overcome this problem, this paper proposes the replacement policy for managing private cache of LLC efficiently. As proposed core-aware cache replacement policy can reconfigure LLC dynamically, hit rate of LLC is increases drastically. Moreover, proposed policy uses 2-bit saturating counters to improve the performance. According to our simulation results, the proposed method can improve hit rates by 9.23% and reduce the access time by 12.85% compared to the conventional method.

• The KIPS Transactions:PartA
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• v.13A no.3
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• pp.191-198
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• 2006

Today's portable electric consumer devices, which are operated by battery, tend to integrate more multimedia processing capabilities. In the multimedia processing devices, multimedia system-on-chips can handle specific algorithms which need intensive processing capabilities and significant power consumption. As a result, the power-efficiency of multimedia processing devices becomes important increasingly. In this paper, we propose a reconfigurable data caching architecture, in which data allocation is constrained by software support, and evaluate its performance and power efficiency. Comparing with conventional cache architectures, power consumption can be reduced significantly, while miss rate of the proposed architecture is very similar to that of the conventional caches. The reduction of power consumption for the reconfigurable data cache architecture shows 33.2%, 53.3%, and 70.4%, when compared with direct-mapped, 2-way, and 4-way caches respectively.

• Proceedings of the Korea Information Processing Society Conference
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• pp.1767-1769
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• 2010

본 논문은 그리드 혹은 클라우드 컴퓨팅환경과 같은 인터넷 기반의 대규모 분산 환경에서 데이터집약적인 작업의 실행에 있어서 확장성을 위해 필수적으로 고려되는 데이터 전송 부하를 분산시키는 기법을 논하고 있다. 우리는 다수의 메모리기반의 데이터 노드를 활용하여 분할기법(Partitioning)을 기반으로 데이터 전송 부하를 줄이고자 하며 다수의 데이터 노드에 실시간으로 최적의 데이터의 양을 공급하는 기법에 대한 이론적인 분석과 시뮬레이션을 통한 성능 검증을 포함하고 있다.