• Title, Summary, Keyword: Device yield

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A Study on 0.13μm Cu/Low-k Process Setup and Yield Improvement (0.13μm Cu/Low-k 공정 Setup과 수율 향상에 관한 연구)

  • Lee, Hyun-Ki;Chang, Eui-Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.20 no.4
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    • pp.325-331
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    • 2007
  • In this study, the inter-metal dielectric material of FSG was changed by low-k material in $0.13{\mu}m$ foundry-compatible technology (FCT) device process based on fluorinated silicate glass (FSG). Black diamond (BD) was used as a low-k material with a dielectric constant of 2.95 for optimization and yield-improvement of the low-k based device process. For yield-improvement in low-k based device process, some problems such as photoresist (PR) poisoning, damage of low-k in etch/ash/cleaning process, and chemical mechanical planarization (CMP) delamination must be solved. The PR poisoning was not observed in BD based device. The pressure in CMP process decreased to 2.8 psi to remove the CMP delamination for Cu-CMP and USG-CMP. $H_2O$ ashing process was selected instead of $O_2$ ashing process due to the lowest condition of low-k damage. NE14 cleaning after ashing process lot the removal of organic residues in vias and trenches was employed for wet process instead of dilute HF (DHF) process. The similar-state of SRAM yield was obtained in Cu/low-k process compared with the conventional $0.13{\mu}m$ FCT device by the optimization of these process conditions.

Effect of Double Grid Cathode in IEC Device (IEC 장치에서 이중 그리드 음극의 영향)

  • Ju, Heung-Jin;Kim, Bong-Seok;Hwang, Hui-Dong;Park, Jeong-Ho;Choi, Seung-Kil;Ko, Kwang-Cheol
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.23 no.9
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    • pp.724-729
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    • 2010
  • We have proposed a new configuration on the cathode structure to improve a neutron yield without the application of external ion sources in an inertial electrostatic confinement (IEC) device. A neutron yield in the IEC device is closely related to the potential well structure generated inside the cathode and is proportional to the ion current. Therefore, the application of a double grid cathode structure to the IEC device is expected to produce a higher ion current and neutron yield than at a single grid cathode due to a high electric field strength generated around the cathode. These possibilities were verified as compared with the ion current calculated from both shape of the single and double grid cathode. Additionally from the results of ion's lives and trajectories examined at various outer cathode voltages and grid cathode configurations by using particle simulations, the validity of the double grid cathode was confirmed.

Thermal Behavior of Flow Pattern Defect and Large Pit in Czochralski Silicon Crystals and Effects of Large Pit upon Device Yield (쵸크랄스키 Silicon 단결정의 Large Pit과 Flow Pattern defect의 열적 거동과 Large Pit의 소자 수율에의 영향)

  • Song, Yeong-Min;Mun, Yeong-Hui;Kim, Jong-O;Jo, Gi-Hyeon
    • Korean Journal of Materials Research
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    • v.11 no.9
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    • pp.781-785
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    • 2001
  • The thermal behavior of Flow Pattern Defect (FPD) and Large Pit (LP) in Czochralski Silicon crystal was investigated by applying high temperature annealing ($\geq$$1100^{\circ}C$) and non-agitated Secco etching. For evaluation of the effect of LP upon device performance/yield, commercial DRAM and ASIC devices were fabricated. The results indicated that high temperature annealing generates LPs whereas it decreases FPD density drastically. However, the origins of FPD and LP seemed to be quite different by not showing any correspondence to their density and the location of LP generation and FPD extinction. By not showing any difference between the performance/yield of devices whose design rule is larger than 0.35 $\mu\textrm{m}$, LP seemed not to have detrimental effects on the performance/yield.

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Thermal behavior of Flow Pattern Defect and Large Pit in Czochralski Silicon Crystals and Their Effects on Device Yield. (Czochralski 법으로 제조된 실리콘 단결정 내의 Flow Pattern Defect와 Large Pit의 열적 거동 및 소자 수율에의 영향)

  • 송영민;조기현;김종오
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • pp.17-20
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    • 1998
  • Thermal behavior of Flow Pattern Defect (FPD) and Large Pit (LP) in Czochralski Silicon crystals was investigated by applying high temperature ($\geq$1100$^{\circ}C$) annealing and non-agitation Secco etching. For evaluation of the effect of LP upon device performance / yield, DRAM and ASIC devices were fabricated. The results indicate that high temperature annealing generates LPs whereas it decreases FPD density drastically, and LP does not have detrimental effects on the performance /

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MEMS Design Flow Based on DFM Concept (DFM 개념을 적용한 MEMS design flow)

  • Han, Seung-Oh;Oh, Park-Kyoun;Silva, Mark da
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.56 no.8
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    • pp.1466-1470
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    • 2007
  • MEMS design flow based on DFM concept is presented and applied to gyroscope design as a test case. It is purposed to contribute to the yield improvement by considering the process-related parameters from the design phase. After defining the performance requirements, the sensitivity analysis should be done on the draft design(s) to find out the key parameters related with the device performance. By doing so, TEG can be designed for the selected process and/or material parameters. Through a set of test runs, the process capability is characterized and the material properties are extracted using the TEG. Then we can estimate the virtual yield of the current process for the designed device by running Monte Carlo analysis where the process and/or material property variations are considered. The estimated yield will make us redesign the device to be more robust or improve the current process to have the smaller variations.

Measuring rheological properties using a slotted plate device

  • Kee, Daniel-De;Kim, Young-Dae;Nguyen, Q. Dzuy
    • Korea-Australia Rheology Journal
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    • v.19 no.2
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    • pp.75-80
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    • 2007
  • The slotted plate technique has previously been shown to be a successful method for directly measuring the static yield stress of suspensions. In this study, we further establish the usefulness of the slotted plate device as a rheometer especially at low shear rates, taking advantage of the extremely low speeds of the slotted plate technique. Newtonian fluids, a shear thinning fluid, and yield stress fluids were tested using the slotted plate device and the results were compared with those from a commercial rheometer using different standard flow geometries. The relationship between the stress on the plate and the viscosity for the slotted plate device obtained by dimensional analysis (drag) predicts a linear relationship between the force at the plate and the plate speed, consistent with the experimental data. The slotted plate device can measure viscosities at very low shear rates. The apparent viscosity - shear-rate data obtained from the slotted plate device are complementary to those obtained using a commercial rheometer. That is : the slotted plate can measure viscosity in the shear rate range $10^{-7}<\dot{\gamma}<10^{-3}\;s^{-1}$, while the commercial rheometer measures viscosity at shear rates higher than $10^{-3}\;s^{-1}$.

Retrofit Yield Spectra-a practical device in seismic rehabilitation

  • Thermou, G.E.;Elnashai, A.S.;Pantazopoulou, S.J.
    • Earthquakes and Structures
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    • v.3 no.2
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    • pp.141-168
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    • 2012
  • The Retrofit Yield Spectrum (RYS) is a new spectrum-based device that relates seismic demand of a retrofitted structure with the fundamental design parameters of the retrofit. This is obtained from superposition of Yield Point Spectra with design charts that summarize in pertinent spectrum-compatible coordinates the attributes of a number of alternative retrofit scenarios. Therefore, once the requirements for upgrading a given structure have been determined, the RYS enable direct insight of the sensitivity of the seismic response of the upgraded structure to the preliminary design decisions made while establishing the retrofit plan. By virtue of their spectrum-based origin, RYS are derived with reference to a single mode of structural vibration; a primary objective is to control the contribution of this mode in the retrofit design so as to produce a desirable distribution of damage at the ultimate limit state by removing soft storey formations and engaging the maximum number of structural members in deformation, in response to the input motion. Calculations are performed with reference to the yield-point, where secant stiffness is proportional to the flexural strength of reinforced concrete members. Derivation and use of the Retrofit Yield Spectra (RYS) refers to the seismic demand expressed either in terms of spectral acceleration, spectral displacement or interstory drift, at yield of the first storey. A reinforced concrete building that has been tested in full scale to a sequence of simulated earthquake excitations is used in the paper as a demonstration case study to examine the effectiveness of the proposed methodology.

Effect of Double Grid Cathode in IEC Device (IEC 장치에서 이중 그리드 음극의 영향)

  • Ju, Heung-Jin;Kim, Bong-Seok;Hwang, Hwui-Dong;Park, Jeong-Ho;Ko, Kwang-Cheol
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • pp.51-51
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    • 2010
  • We have proposed a new configuration for the improvement of neutron yield without the application of external ion sources in an inertial electrostatic confinement (IEC) device. The application of a double grid cathode to the IEC device is expected to generate a higher ion current than a single grid cathode. This paper verifies the effect of the double grid cathode by both fluid and particle simulation. Through the fluid simulation the optimal shape and applied voltage of the double grid cathode is determined, and through the particle simulation the usefulness of that is confirmed.

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Design of Energy Absorbing Braces (가새형 소성변형감쇠기의 설계 방법에 관한 연구)

  • 김진구;이강준
    • Proceedings of the Computational Structural Engineering Institute Conference
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    • pp.265-272
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    • 2000
  • Unbond brace hysteretic dampers are generally used to prevent or decrease structural damage in buildings subjected to strong earthquake by its energy dissipating hysteretic behavior. According to a previous research, the optimum ratio of device yield strength to story yield strength of the combined system has been identified as the most important parameter for characterizing the performance of this device. In this research, the validity and the applicability of the previous research has been investigated and a new approach has been proposed through earthquake response analysis of a steel structure installed with unbond brace type hysteretic damper.

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The resistance characterization of OTP device using anti-fuse MOS capacitor after programming (안티퓨즈 MOS capacitor를 이용한 OTP 소자의 프로그래밍 후의 저항특성)

  • Chang, Sung-Keun;Kim, Youn-Jang
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.13 no.6
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    • pp.2697-2701
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    • 2012
  • The yield of OTP devices using anti-fuse MOS capacitor have been affected by the input resistance, the size of the pass transistor and the read transistor, and the readout voltage of programed cell. To investigate the element which gives an effect to yield, we analyze the full map data of the resistance characterization of OTP device and those data in a various experimental condition. As a result, we got the optimum conditions which is necessary to the yield improvement. The optimum conditions are as follows: Input resistance is 50 ohms, the channel length of pass transistor is 10um, read voltage is 2.8 volt, respectively.