• Title, Summary, Keyword: Double channel

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Effects of Channel Thickness on Oxide Thin Film Transistor with Double-Stacked Channel Layer

  • Lee, Kimoon;Kim, Yong-Hoon;Yoon, Sung-Min;Kim, Jiwan;Oh, Min Suk
    • Journal of the Korean Physical Society
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    • v.71 no.9
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    • pp.561-564
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    • 2017
  • To improve the field effect mobility and control the threshold voltage ($V_{th}$) of oxide thin film transistors (TFTs), we fabricated the oxide TFTs with double-stacked channel layers which consist of thick Zn-Sn-O (ZTO) and very thin In-Zn-O (IZO) layers. We investigated the effects of the thickness of thin conductive layer and the conductivity of thick layer on oxide TFTs with double-stacked channel layer. When we changed the thickness of thin conductive IZO channel layer, the resistivity values were changed. This resistivity of thin channel layer affected on the saturation field effect mobility and the off current of TFTs. In case of the thick ZTO channel layer which was deposited by sputtering in $Ar:O_2=10:1$, the device showed better performances than that which was deposited in $Ar:O_2=1:1$. Our TFTs showed high mobility (${\mu}_{FE}$) of ${\sim}40.7cm^2/Vs$ and $V_{th}$ of ~ 4.3 V. We assumed that high mobility and the controlled $V_{th}$ were caused by thin conductive IZO layer and thick stable ZTO layer. Therefore, this double-stacked channel structure can be very promising way to improve the electrical characteristics of various oxide thin film transistors.

Non-Overlapped Single/Double Gate SOI/GOI MOSFET for Enhanced Short Channel Immunity

  • Sharma, Sudhansh;Kumar, Pawan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.9 no.3
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    • pp.136-147
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    • 2009
  • In this paper we analyze the influence of source/drain (S/D) extension region design for minimizing short channel effects (SCEs) in 25 nm gate length single and double gate Silicon-on-Insulator (SOI) and Germanium-on-Insulator (GOI) MOSFETs. A design methodology, by evaluatingm the ratio of the effective channel length to the natural length for the different devices (single or double gate FETs) and technology (SOI or GOI), is proposed to minimize short channel effects (SCEs). The optimization of non-overlapped gate-source/drain i.e. underlap channel architecture is extremely useful to limit the degradation in SCEs caused by the high permittivity channel materials like Germanium as compared to that exhibited in Silicon based devices. Subthreshold slope and Drain Induced Barrier Lowering results show that steeper S/D gradients along with wider spacer regions are needed to suppress SCEs in GOI single/double gate devices as compared to Silicon based MOSFETs. A design criterion is developed to evaluate the minimum spacer width associated with underlap channel design to limit SCEs in SOI/GOI MOSFETs.

The Analysis of Breakdown Voltage for the Double-gate MOSFET Using the Gaussian Doping Distribution

  • Jung, Hak-Kee
    • Journal of information and communication convergence engineering
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    • v.10 no.2
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    • pp.200-204
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    • 2012
  • This study has presented the analysis of breakdown voltage for a double-gate metal-oxide semiconductor field-effect transistor (MOSFET) based on the doping distribution of the Gaussian function. The double-gate MOSFET is a next generation transistor that shrinks the short channel effects of the nano-scaled CMOSFET. The degradation of breakdown voltage is a highly important short channel effect with threshold voltage roll-off and an increase in subthreshold swings. The analytical potential distribution derived from Poisson's equation and the Fulop's avalanche breakdown condition have been used to calculate the breakdown voltage of a double-gate MOSFET for the shape of the Gaussian doping distribution. This analytical potential model is in good agreement with the numerical model. Using this model, the breakdown voltage has been analyzed for channel length and doping concentration with parameters such as projected range and standard projected deviation of Gaussian function. As a result, since the breakdown voltage is greatly changed for the shape of the Gaussian function, the channel doping distribution of a double-gate MOSFET has to be carefully designed.

Analytical Model for the Threshold Voltage of Long-Channel Asymmetric Double-Gate MOSFET based on Potential Linearity (전압분포의 선형특성을 이용한 Long-Channel Asymmetric Double-Gate MOSFET의 문턱전압 모델)

  • Yang, Hee-Jung;Kim, Ji-Hyun;Son, Ae-Ri;Kang, Dae-Gwan;Shin, Hyung-Soon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.2
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    • pp.1-6
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    • 2008
  • A compact analytical model of the threshold voltage for long-channel Asymmetric Double-Gate(ADG) MOSFET is presented. In contrast to the previous models, channel doping and carrier quantization are taken into account. A more compact model is derived by utilizing the potential distribution linearity characteristic of silicon film at threshold. The accuracy of the model is verified by comparisons with numerical simulations for various silicon film thickness, channel doping concentration and oxide thickness.

Analysis of Short Channel Effects Using Analytical Transport Model For Double Gate MOSFET

  • Jung, Hak-Kee
    • Journal of information and communication convergence engineering
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    • v.5 no.1
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    • pp.45-49
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    • 2007
  • The analytical transport model in subthreshold regime for double gate MOSFET has been presented to analyze the short channel effects such as subthreshold swing, threshold voltage roll-off and drain induced barrier lowering. The present approach includes the quantum tunneling of carriers through the source-drain barrier. Poisson equation is used for modeling thermionic emission current, and Wentzel-Kramers-Brillouin approximations are applied for modeling quantum tunneling current. This model has been used to investigate the subthreshold operations of double gate MOSFET having the gate length of the nanometer range with ultra thin gate oxide and channel thickness under sub-20nm. Compared with results of two dimensional numerical simulations, the results in this study show good agreements with those for subthreshold swing and threshold voltage roll-off. Note the short channel effects degrade due to quantum tunneling, especially in the gate length of below 10nm, and DGMOSFETs have to be very strictly designed in the regime of below 10nm gate length since quantum tunneling becomes the main transport mechanism in the subthreshold region.

Optimizing Effective Channel Length to Minimize Short Channel Effects in Sub-50 nm Single/Double Gate SOI MOSFETs

  • Sharma, Sudhansh;Kumar, Pawan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.8 no.2
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    • pp.170-177
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    • 2008
  • In the present work a methodology to minimize short channel effects (SCEs) by modulating the effective channel length is proposed to design 25 nm single and double gate-source/drain underlap MOSFETs. The analysis is based on the evaluation of the ratio of effective channel length to natural/ characteristic length. Our results show that for this ratio to be greater than 2, steeper source/drain doping gradients along with wider source/drain roll-off widths will be required for both devices. In order to enhance short channel immunity, the ratio of source/drain roll-off width to lateral straggle should be greater than 2 for a wide range of source/drain doping gradients.

A Novel Epsilon Near Zero Tunneling Circuit Using Double-Ridge Rectangular Waveguide

  • Kim, Byung-Mun;Son, Hyeok-Woo;Hong, Jae-Pyo;Cho, Young-Ki
    • Journal of electromagnetic engineering and science
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    • v.14 no.1
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    • pp.36-42
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    • 2014
  • In this paper, an epsilon near zero (ENZ) tunneling circuit using a double-ridge rectangular waveguide (RWG) is proposed for the miniaturization of a waveguide component. The proposed ENZ channel and is located in the middle of the input-output RWG (IORWG). The ratio of the height to the width of the channel waveguide is very small compared to the IORWG. By properly adjusting the ridge dimensions, the tunneling frequency of the proposed ENZ channel can be lowered to near the cut-off frequency of the IORWG. For the proposed ENZ tunneling circuit, the approach adopted for extracting the effective permittivity, effective permeability;normalized effective wave impedance, and propagation constant from the simulated scattering parameters was explained. The extracted parameters verified that the proposed channel is an ENZ channel and electromagnetic energy is tunneling through the channel. Simulation and measurement results of the fabricated ENZ channel structure agreed.

Investigation of shear lag effect on tension members fillet-welded connections consisting of single and double channel sections

  • Barkhori, Moien;Maleki, Shervin;Mirtaheri, Masoud;Nazeryan, Meissam;Kolbadi, S.Mahdi S.
    • Structural Engineering and Mechanics
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    • v.74 no.3
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    • pp.445-455
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    • 2020
  • Shear lag phenomenon has long been taken into consideration in various structural codes; however, the AISC provisions have not proposed any specific equation to calculate the shear lag ratio in some cases such as fillet-welded connections of front-to-front double channel sections. Moreover, those equations and formulas proposed by structural codes are based on the studies that were conducted on riveted and bolted connections, and can be applied to single channel sections whilst using them for fillet-welded double channels would be extremely conservative due to the symmetrical shape and the fact that bending moments will not develop in the gusset plate, resulting in less stress concentration. Numerical models are used in the present study to focus on parametric investigation of the shear lag effect on fillet-welded tension connection of double channel section to a gusset plate. The connection length, the eccentricity of axial load, the free length and the thickness of gusset plate are considered as the key factors in this study. The results are then compared to the estimates driven from the AISC-LRFD provisions and alternative equations are proposed.

Analysis of Short-Channel Effect due to the 2D QM effect in the poly gate of Double-Gate MOSFETs (폴리게이트의 양자 효과에 따른 Double-Gate MOSFET의 단채널 효과 분석)

  • 박지선;신형순
    • Proceedings of the IEEK Conference
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    • pp.691-694
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    • 2003
  • Density gradient method is used to analyze the quantum effect in MOSFET, Quantization effect in the poly gate leads to a negative threshold voltage shift, which is opposed to the positive shift caused by quantization effect in the channel. Quantization effects in the poly gate are investigated using the density gradient method, and the impact on the short channel effect of double gate device is more significant.

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Performance Analysis of Double Binary Turbo Coded PPM-TH UWB Systems (이중 이진 터보 부호화된 펄스 위치변조-시간도약 초광대역 무선 통신 시스템의 성능 분석)

  • Kim, Eun-Cheol;Kwak, Do-Young;Park, Jae-Sung;Kim, Jin-Young
    • 한국정보통신설비학회:학술대회논문집
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    • pp.429-432
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    • 2008
  • In this paper, performance of a double binary turbo coded ultra wide band (UWB) system is analyzed and simulated in an indoor wireless channel. Binary pulse position modulation-time hopping (BPPM-TH) signals are considered. The indoor wireless channel is modeled as a modified Saleh and Valenzuela (SV) channel. The performance is evaluated in terms of bit error probability (BER). From the simulation results, it is seen that double binary turbo coding offers considerable coding gain with reasonable encoding complexity. It is also demonstrated that the performance of the UWB system can be substantially improved by increasing the number of iterations.

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