• Title, Summary, Keyword: Dry etching

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A Via-Hole Process for GaAs MMIC's using Two-Step Dry Etching (2단계 건식식각에 의한 GaAs Via-Hole 형성 공정)

  • 정문식;김흥락;이지은;김범만;강봉구
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.30A no.1
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    • pp.16-22
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    • 1993
  • A via-hole process for reproducible and reliable GaAs MMIC fabrication is described. The via-hole etching process consists of two step dry etching. During the first etching step a BC $I_{3}$/C $I_{2}$/Ar gas mixure is used to achieve high etch rate and small lateral etching. In the second etching step. CC $L_{2}$ $F_{2}$ gas is used to achieve selective etching of the GaAs substrate with respect to the front side metal layer. Via holes are formed from the backside of a 100$\mu$m thick GaAs substrate that has been evaporated initially with 500.angs. thick chromium and subsequently a 2000.angs. thick gold layer. The fabricated via holes are electroplated with gold (~20$\mu$m thick) to form via connections. The results show that established via-hole process is satisfactory for GaAs MMIC fabrication.

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A study on platinum dry etching using a cryogenic magnetized inductively coupled plasma (극저온 자화 유도 결합 플라즈마를 이용한 Platinum 식각에 관한 연구)

  • 김진성;김정훈;김윤택;황기웅;주정훈;김진웅
    • Journal of the Korean Vacuum Society
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    • v.8 no.4A
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    • pp.476-481
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    • 1999
  • Characteristics of platinum dry etching were investigated in a cryogenic magnetized inductively coupled plasma (MICP). The problem with platinum etching is the redeposition of sputtered platinum on the sidewall. Because of the redeposits on the sidewall, the etching of patterned platinum structure produces feature sizes that exceed the original dimension of the PR size and the etch profile has needle-like shape [1]. The main object of this study was to investigate a new process technology for fence-free Pt etching As bias voltage increased, the height of fence was reduced. In cryogenic etching, the height of fence was reduced to 20% at-$190^{\circ}C$ compared with that of room temperature, however the etch profile was not still fence-free. In Ar/$SF_6$ Plasma, fence-free Pt etching was possible. As the ratio of $SF_6$ gas flow is more than 14% of total gas flow, the etch profile had no fence. Chemical reaction seemed to take place in the etch process.

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A Dry-patterned Cu(Mg) Alloy Film as a Gate Electrode in a Thin Film Transistor Liquid Crystal Displays (TFT- LCDs) (TFT-LCDs 게이트 전극에 적용한 Cu(Mg) 합금 박막의 건식식각)

  • Yang Heejung;Lee Jaegab
    • Korean Journal of Materials Research
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    • v.14 no.1
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    • pp.46-51
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    • 2004
  • The annealing of a Cu(4.5at.% Mg)/$SiO_2$/Si structure in ambient $O_2$, at 10 mTorr, and $300-500^{\circ}C$, allows for the outdiffusion of the Mg to the Cu surface, forming a thin MgO (15 nm) layer on the surface. The surface MgO layer was patterned, and successfully served as a hard mask, for the subsequent dry etching of the underlying Mg-depleted Cu films using an $O_2$ plasma and hexafluoroacetylacetone [H(hfac)] chemistry. The resultant MgO/Cu structure, with a taper slope of about $30^{\circ}C$ shows the feasibility of the dry etching of Cu(Mg) alloy films using a surface MgO mask scheme. A dry-etched Cu(4.5at.% Mg) gate a-Si:H TFT has a field effect mobility of 0.86 $\textrm{cm}^2$/Vs, a subthreshold swing of 1.08 V/dec, and a threshold voltage of 5.7 V. A novel process for the dry etching of Cu(Mg) alloy films, which eliminates the use of a hard mask, such as Ti, and results in a reduction in the process steps is reported for the first time in this work.

Laser Direct Ory Etching for $Al_{0.3}Ga_{0.7}As/GaAs$ Multi-layer Structures ($Al_{0.3}Ga_{0.7}As/GaAs$ 다층구조의 레이저 직접 건식에칭)

  • Park, Se-Ki;Lee, Cheon;Kim, Seong-Il;Kim, Eun-Kyu;Min, Suk-Ki
    • Proceedings of the KIEE Conference
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    • pp.1980-1981
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    • 1996
  • Laser direct dry etching is a new technique in semiconductor processing which has a lot of advantage, including decrease of etching-induced damage, maskless, photoresistiess, and high selectivity. This study presents characteristics of a laser direct dry etching for $Al_{0.3}Ga_{0.7}As/GaAs$ multi-layer structures for the first time. In this study, we were able to obtain the unusual aching profiles. The cross sectional analysis of etched groove was peformed for reaction characteristics and their applications.

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A study on Silicon dry Etching for Solar Cell Fabrication Using Hollow Cathode Plasma System (태양전지 제작을 위한 Hollow Cathode Plasma System의 실리콘 건식식각에 관한 연구)

  • ;Suresh Kumar Dhungel
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.53 no.2
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    • pp.62-66
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    • 2004
  • This paper investigated the characteristics of a newly developed high density hollow cathode plasma (HCP) system and its application for the etching of silicon wafers. We used SF$_{6}$ and $O_2$ gases in the HCP dry etch process. Silicon etch rate of $0.5\mu\textrm{m}$/min was achieved with $SF_6$$O_2$plasma conditions having a total gas pressure of 50mTorr, and RF power of 100 W. This paper presents surface etching characteristics on a crystalline silicon wafer and large area cast type multicrystlline silicon wafer. The results of this experiment can be used for various display systems such as thin film growth and etching for TFT-LCDs, emitter tip formations for FEDs, and bright plasma discharge for PDP applications.s.

RIE에서 $C_3F_6$ 가스를 이용한 $Si_3N_4$ 식각공정 개발

  • Jeon, Seong-Chan;Gong, Dae-Yeong;Jeong, Dong-Geon;Choe, Ho-Yun;Kim, Bong-Hwan;Jo, Chan-Seop;Lee, Jong-Hyeon
    • Proceedings of the Korean Vacuum Society Conference
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    • pp.328-329
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    • 2012
  • $SF_6$ gas는 반도체 및 디스플레이 제조공정 중 Dry etch과정에서 널리 사용되는 gas로 자연적으로 존재하는 것이 아닌 사용 목적에 맞춰 인위적으로 제조된 gas이다. 디스플레이 산업에서 $SF_6$ gas가 사용되는 Dry etch 공정은 주로 ${\alpha}$-Si, $Si_3N_4$ 등 Si계열의 박막을 etch하는데 사용된다. 이러한 Si 계열의 박막을 식각하기 위해서는 fluorine, Chlorine 등이 사용된다. fluorine계열의 gas로는 $SF_6$ gas가 대표적이다. 하지만 $SF_6$ gas는 대표적인 온실가스로 지구 온난화의 주범으로 주목받고 있다. 세계적으로 온실가스의 규제에 대한 움직임이 활발하고, 대한민국은 2020년까지 온실가스 감축목표를 '배출전망치(BAU)대비 30% 감축으로' 발표하였다. 따라서 디스플레이 및 반도체 공정에는 GWP (Global warming Potential)에 적용 가능한 대체 가스의 연구가 필요한 상황이다. 온실가스인 $SF_6$를 대체하기 위한 방법으로 GWP가 낮은 $C_3F_6$가스를 이용하여 $Si_3N_4$를 Dry etching 방법인 RIE (Reactive Ion Etching)공정을 한 후 배출되는 가스를 측정하였다. 4인치 P-type 웨이퍼 위에 PECVD (Plasma Enhanced Chemical Vapor Deposition)장비를 이용하여 $Si_3N_4$를 200 nm 증착하였고, Photolithography공정을 통해 Patterning을 한 후 RIE공정을 수행하였다. RIE는 Power : 300 W, Flow rate : 30 sccm, Time : 15 min, Temperature : $15^{\circ}C$, Pressure : Open과 같은 조건으로 공정을 수행하였다. 그리고 SEM (Scanning Electron Microscope)장비를 이용하여 Etching된 단면을 관찰하여 단차를 확인하였다. 또한 Etching 전후 배출가스를 포집하여 GC-MS (Gas Chromatograph-Mass Spectrophotometry)를 측정 및 비교하였다. Etching 전의 경우에는 $N_2$, $O_2$ 등의 가스가 검출되었고, $C_3F_6$ 가스를 이용해 etching 한 후의 경우에는 $C_3F_6$ 계열의 가스가 검출되었다.

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A Study on Etching of $UO_2$, Co, and Mo Surface with R.F. Plasma Using $CF_4\;and\;O_2$

  • Kim Yong-Soo;Seo Yong-Dae
    • Nuclear Engineering and Technology
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    • v.35 no.6
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    • pp.507-514
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    • 2003
  • Recently dry decontamination/surface-cleaning technology using plasma etching has been focused in the nuclear industry. In this study, the applicability of this new dry processing technique are experimentally investigated by examining the etching reaction of $UO_2$, Co, and Mo in r.f. plasma with the etchant gas of $CF_4/O_2$ mixture. $UO_2$ is chosen as a representing material for uranium and TRU (TRans-Uranic) compounds while metallic Co and Mo are selected because they are the principal contaminants in the used metallic nuclear components such as valves and pipes made of stainless steel or inconel. Results show that in all cases maximum etching rate is achieved when the mole fraction of $UO_2\;in\;CF_4/O_2$ mixture gas is $20\%$, regardless of temperature and r.f. power. In case of $UO_2$, the highest etching reaction rate is greater than 1000 monolayers/min. at $370^{\circ}C$ under 150 W r.f. power which is equivalent to $0.4{\mu}m/min$. As for Co, etching reaction begins to take place significantly when the temperature exceeds $350^{\circ}C$. Maximum etching rate achieved at $380^{\circ}C\;is\;0.06{\mu}m/min$. Mo etching reaction takes place vigorously even at relatively low temperature and the reaction rate increases drastically with increasing temperature. Highest etching rate at $380^{\circ}C\;is\;1.9{\mu}m/min$. According to OES (Optical Emission Spectroscopy) and AES (Auger Electron Spectroscopy) analysis, primary reaction seems to be a fluorination reaction, but carbonyl compound formation reaction may assist the dominant reaction, especially in case of Co and Mo. Through this basic study, the feasibility and the applicability of plasma decontamination technique are demonstrated.

Study of sand blaster dry etched glass wafer surface for micro device package (샌드 블러스터로 건식 식각한 마이크로 소자 패키지용 유리 웨이퍼의 표면 연구)

  • Kim, Jong-Seok;Nam, Kwang-Woo;Choa, Sung-Hoon;Kwon, Jae-Hong;Ju, Byeong-Kwon
    • Journal of Sensor Science and Technology
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    • v.15 no.4
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    • pp.245-250
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    • 2006
  • In this paper, glass cap wafer for MEMS device package is fabricated by using sand blaster dry etcher and Its surface is studied. The surface of dry etched glass is analyzed by using SEM, and many glass particles and micro cracks are observed. If these kind of particles were dropped from glass to the surface of device, It would make critical failure to the operation of device. So, several cleaning and etching methods are induced to remove these kinds of dormant failure mode and optimized condition is found out.

Electrical Characterization of Nano SOI Wafer by Pseudo MOSFET (Pseudo MOSFET을 이용한 Nano SOI 웨이퍼의 전기적 특성분석)

  • Bae, Young-Ho;Kim, Byoung-Gil;Kwon, Kyung-Wook
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.18 no.12
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    • pp.1075-1079
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    • 2005
  • The Pseudo MOSFET measurements technique has been used for the electrical characterization of the nano SOI wafer. Silicon islands for the Pseudo MOSFET measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo MOSFET were not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device were dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100 nm SOI was obtained by thinning the silicon film of standard thick SOI wafer. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching Process dependency is greater in the thinner SOI wafer.