• Title, Summary, Keyword: Dry etching

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Copper Interconnection and Flip Chip Packaging Laboratory Activity for Microelectronics Manufacturing Engineers

  • Moon, Dae-Ho;Ha, Tae-Min;Kim, Boom-Soo;Han, Seung-Soo;Hong, Sang-Jeen
    • Proceedings of the Korean Vacuum Society Conference
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    • pp.431-432
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    • 2012
  • In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

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Study of the Reliability Characteristics of the ONON(oxide-nitride-oxide-nitride) Inter-Poly Dielectrics in the Flash EEPROM cells (플래시 EEPROM 셀에서 ONON(oxide-nitride-oxide-nitride) Inter-Poly 유전체막의 신뢰성 연구)

  • Shin, Bong-Jo;Park, Keun-Hyung
    • Journal of the Korean Institute of Telematics and Electronics D
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    • v.36D no.10
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    • pp.17-22
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    • 1999
  • In this paper, the results of the studies about a new proposal where the ONON(oxide-nitride-oxide-nitride) layer instead of the conventional ONO(oxide-nitride-oxide) layer is used as the IPD(inter-poly-dielectrics) layer to improve the data retention problem in the Flash EEPROM cell, have been discussed. For these studies, the stacked-gate Flash EEPROM cell with an about 10nm thick gate oxide and on ONO or ONON IPD layer have been fabricated. The measurement results have shown that the data retention characteristics of the devices with the ONO IPD layer are significantly degraded with an activation energy of 0.78 eV. which is much lower than the minimum value (1.0 eV) required for the Flash EEPROM cell. This is believed to be due to the partial or whole etching of the top oxide of the IPD layer during the cleaning process performed just prior to the dry oxidation process to grow the gate oxide of the peripheral MOSFET devices. Whereas the data retention characteristics of the devices with the ONON IPD layer have been found to be much (more than 50%) improved with an activation energy of 1.10 eV. This must be because the thin nitride layer on the top oxide layer in the ONON IPD layer protected the top oxide layer from being etched during the cleaning process.

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Effects of DC Biases and Post-CMP Cleaning Solution Concentrations on the Cu Film Corrosion

  • Lee, Yong-K.;Lee, Kang-Soo
    • Corrosion Science and Technology
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    • v.9 no.6
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    • pp.276-280
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    • 2010
  • Copper(Cu) as an interconnecting metal layer can replace aluminum (Al) in IC fabrication since Cu has low electrical resistivity, showing high immunity to electromigration compared to Al. However, it is very difficult for copper to be patterned by the dry etching processes. The chemical mechanical polishing (CMP) process has been introduced and widely used as the mainstream patterning technique for Cu in the fabrication of deep submicron integrated circuits in light of its capability to reduce surface roughness. But this process leaves a large amount of residues on the wafer surface, which must be removed by the post-CMP cleaning processes. Copper corrosion is one of the critical issues for the copper metallization process. Thus, in order to understand the copper corrosion problems in post-CMP cleaning solutions and study the effects of DC biases and post-CMP cleaning solution concentrations on the Cu film, a constant voltage was supplied at various concentrations, and then the output currents were measured and recorded with time. Most of the cases, the current was steadily decreased (i.e. resistance was increased by the oxidation). In the lowest concentration case only, the current was steadily increased with the scarce fluctuations. The higher the constant supplied DC voltage values, the higher the initial output current and the saturated current values. However the time to be taken for it to be saturated was almost the same for all the DC supplied voltage values. It was indicated that the oxide formation was not dependent on the supplied voltage values and 1 V was more than enough to form the oxide. With applied voltages lower than 3 V combined with any concentration, the perforation through the oxide film rarely took place due to the insufficient driving force (voltage) and the copper oxidation ceased. However, with the voltage higher than 3 V, the copper ions were started to diffuse out through the oxide film and thus made pores to be formed on the oxide surface, causing the current to increase and a part of the exposed copper film inside the pores gets back to be oxidized and the rest of it was remained without any further oxidation, causing the current back to decrease a little bit. With increasing the applied DC bias value, the shorter time to be taken for copper ions to be diffused out through the copper oxide film. From the discussions above, it could be concluded that the oxide film was formed and grown by the copper ion diffusion first and then the reaction with any oxidant in the post-CMP cleaning solution.

Low Resistance Indium-based Ohmic Contacts to N-face n-GaN for GaN-based Vertical Light Emitting Diodes (GaN계 수직형 발광 다이오드를 위한 N-face n-GaN의 인듐계 저저항 오믹접촉 연구)

  • Kang, Ki Man;Park, Min Joo;Kwak, Joon Seop;Kim, Hyun Soo;Kwon, Kwang Woo;Kim, Young Ho
    • Korean Journal of Metals and Materials
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    • v.48 no.5
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    • pp.456-461
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    • 2010
  • We investigated the In-based ohmic contacts on Nitrogen-face (N-face) n-type GaN, as well as Ga-face n-type GaN, for InGaN-based vertical Light Emitting Diodes (LEDs). For this purpose, we fabricated Circular Transfer Length Method (CTLM) patterns on the N-face n-GaN that were prepared by using a laser-lift off method, as well as on the Ga-face n-GaN that were prepared by using a dry etching method. Then, In/transparent conducting oxide (TCO) and In/TiW schemes were deposited on the CTLM in order for low resistance ohmic contacts to form. The In/TCO scheme on the Ga-face n-GaN showed high specific contact resistance, while the minimum specific contact resistance was only 3${\times}$10$^{-2}$ $\Omega$-cm$^{2}$ after annealing at 300${^{\circ}C}$, which can be attributed to the high sheet resistance of the TCO layer. In contrast, the In/TiW scheme on the Ga-face n-GaN produced low specific contact resistance of 2.1${\times}$10$^{5}$ $\Omega$-cm$^{2}$ after annealing at 500${^{\circ}C}$ for 1 min. In addition, the In/TiW scheme on the N-face n-GaN also resulted in a low specific contact resistance of 2.2${\times}$10$^{-4}$ $\Omega$-cm$^{2}$ after annealing at 300${^{\circ}C}$. These results suggest that both the Ga-face n-GaN and N-face n-GaN.

The characteristic of InGaN/GaN MQW LED by different diameter in selective area growth method (선택성장영역 크기에 따른 InGaN/GaN 다중양자우물 청색 MOCVD-발광다이오드 소자의 특성)

  • Bae, Seon-Min;Jeon, Hun-Soo;Lee, Gang-Seok;Jung, Se-Gyo;Yoon, Wi-Il;Kim, Kyoung-Hwa;Yang, Min;Yi, Sam-Nyung;Ahn, Hyung-Soo;Kim, Suck-Whan;Yu, Young-Moon;Ha, Hong-Ju
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.22 no.1
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    • pp.5-10
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    • 2012
  • In general, the fabrications of the LEDs with mesa structure are performed grown by MOCVD method. In order to etch and separate each chips, the LEDs are passed the RIE and scribing processes. The RIE process using plasma dry etching occur some problems such as defects, dislocations and the formation of dangling bond in surface result in decline of device characteristic. The SAG method has attracted considerable interest for the growth of high quality GaN epi layer on the sapphire substrate. In this paper, the SAG method was introduced for simplification and fabrication of the high quality epi layer. And we report that the size of selective area do not affect the characteristics of original LED. The diameter of SAG circle patterns were choose as 2500, 1000, 350, and 200 ${\mu}m$. The SAG-LEDs were measured to obtain the device characteristics using by SEM, EL and I-V. The main emission peaks of 2500, 1000, 350, and 200 ${\mu}m$ were 485, 480, 450, and 445 nm respectively. The chips of 350, 200 ${\mu}m$ diameter were observed non-uniform surface and resistance was higher than original LED, however, the chips of 2500, 1000 ${\mu}m$ diameter had uniform surface and current-voltage characteristics were better than small sizes. Therefore, we suggest that the suitable diameter which do not affect the characteristic of original LED is more than 1000 ${\mu}m$.