• Title, Summary, Keyword: Dry etching

Search Result 395, Processing Time 0.039 seconds

The Wet and Dry Etching Process of Thin Film Transistor (박막트랜지스터의 습식 및 건식 식각 공정)

  • Park, Choon-Sik;Hur, Chang-Wu
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.13 no.7
    • /
    • pp.1393-1398
    • /
    • 2009
  • Conventionally, etching is first considered for microelectronics fabrication process and is specially important in process of a-Si:H thin film transistor for LCD. In this paper, we stabilize properties of device by development of wet and dry etching process. The a-Si:H TFTs of this paper is inverted staggered type. The gate electrode is lower part. The gate electrode is formed by patterning with length of 8 ${\mu}$m${\sim}$16 ${\mu}$m and width of 80${\sim}$200 ${\mu}$m after depositing with gate electrode (Cr) 1500 ${\AA}$under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photo resistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN:H (2000 ${\mu}$m), a-Si:H(2000 ${\mu}$m) and n+a-Si:H (500 ${\mu}$m), We have deposited n-a-Si:H, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. In the fabricated TFT, the most frequent problems are over and under etching in etching process. We were able to improve properties of device by strict criterion on wet, dry etching and cleaning process.

Dry Etching of Polysilicon in Hbr/O2 Inductively Coupled Plasmas (Hbr/O2 유도결합 플라즈마를 이용한 폴리실리콘 건식식각)

  • 범성진;송오성;이혜영;김종준
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.17 no.1
    • /
    • pp.1-6
    • /
    • 2004
  • Dry etch characteristics of polysilicon with HBr/O$_2$ inductively coupled plasma (ICP) have been investigated. We determined etch late, uniformity, etch profiles, and selectivity with analyzing the cross-sectional scanning electron microscopy images obtained from top, center, bottom, right, and left positions. The etch rate of polysilicon was about 2500 $\AA$/min, which meets with the mass production for devices. The wafer level etch uniformity was within $\pm$5 %. Etch profile showed 90$^{\circ}$ slopes without notches. The selectivity over photoresist was between 2:1∼4.5:1, depending on $O_2$ flow rate. The HBr-ICP etching showed higher PR selectivity, and sharper profile than the conventional Cl$_2$-RIE.

Dry Etching of GaAs in a Planar Inductively Coupled BCl3 Plasma (BCl3 평판형 유도결합 플라즈마를 이용한 GaAs 건식식각)

  • Lim, Wan-tea;Baek, In-kyoo;Jung, Pil-gu;Lee, Je-won;Cho, Guan-Sik;Lee, Joo-In;Cho, Kuk-San;Pearton, S.J.
    • Korean Journal of Materials Research
    • /
    • v.13 no.4
    • /
    • pp.266-270
    • /
    • 2003
  • We studied BCl$_3$ dry etching of GaAs in a planar inductively coupled plasma system. The investigated process parameters were planar ICP source power, chamber pressure, RIE chuck power and gas flow rate. The ICP source power was varied from 0 to 500 W. Chamber pressure, RIE chuck power and gas flow rate were controlled from 5 to 15 mTorr, 0 to 150 W and 10 to 40 sccm, respectively. We found that a process condition at 20 sccm $BCl_3$ 300 W ICP, 100 W RIE and 7.5 mTorr chamber pressure gave an excellent etch result. The etched GaAs feature depicted extremely smooth surface (RMS roughness < 1 nm), vertical sidewall, relatively fast etch rate (> $3000\AA$/min) and good selectivity to a photoresist (> 3 : 1). XPS study indicated a very clean surface of the material after dry etching of GaAs. We also noticed that our planar ICP source was successfully ignited both with and without RIE chuck power, which was generally not the case with a typical cylindrical ICP source, where assistance of RIE chuck power was required for turning on a plasma and maintaining it. It demonstrated that the planar ICP source could be a very versatile tool for advanced dry etching of damage-sensitive compound semiconductors.

The Effect of Mask Patterns on Microwire Formation in p-type Silicon (P-형 실리콘에서 마이크로 와이어 형성에 미치는 마스크 패턴의 영향)

  • Kim, Jae-Hyun;Kim, Kang-Pil;Lyu, Hong-Kun;Woo, Sung-Ho;Seo, Hong-Seok;Lee, Jung-Ho
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • /
    • pp.418-418
    • /
    • 2008
  • The electrochemical etching of silicon in HF-based solutions is known to form various types of porous structures. Porous structures are generally classified into three categories according to pore sizes: micropore (below 2 nm in size), mesopore (2 ~ 50 nm), and macropore (above 50 nm). Recently, the formation of macropores has attracted increasing interest because of their promising characteristics for an wide scope of applications such as microelectromechanical systems (MEMS), chemical sensors, biotechnology, photonic crystals, and photovoltaic application. One of the promising applications of macropores is in the field of MEMS. Anisotropic etching is essential step for fabrication of MEMS. Conventional wet etching has advantages such as low processing cost and high throughput, but it is unsuitable to fabricate high-aspect-ratio structures with vertical sidewalls due to its inherent etching characteristics along certain crystal orientations. Reactive ion dry etching is another technique of anisotropic etching. This has excellent ability to fabricate high-aspect-ratio structures with vertical sidewalls and high accuracy. However, its high processing cost is one of the bottlenecks for widely successful commercialization of MEMS. In contrast, by using electrochemical etching method together with pre-patterning by lithographic step, regular macropore arrays with very high-aspect-ratio up to 250 can be obtained. The formed macropores have very smooth surface and side, unlike deep reactive ion etching where surfaces are damaged and wavy. Especially, to make vertical microwire or nanowire arrays (aspect ratio = over 1:100) on silicon wafer with top-down photolithography, it is very difficult to fabricate them with conventional dry etching. The electrochemical etching is the most proper candidate to do it. The pillar structures are demonstrated for n-type silicon and the formation mechanism is well explained, while such a experimental results are few for p-type silicon. In this report, In order to understand the roles played by the kinds of etching solution and mask patterns in the formation of microwire arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, dimethyl sulfoxide (DMSO), iso-propanol, and mixtures of HF with water on the structure formation on monocrystalline p-type silicon with a resistivity with 10 ~ 20 $\Omega{\cdot}cm$. The different morphological results are presented according to mask patterns and etching solutions.

  • PDF

Microfabrication of Submicron-size Hole on the Silicon Substrate using ICP etching

  • Lee, J.W.;Kim, J.W.;Jung, M.Y.;Kim, D.W.;Park, S.S.
    • Proceedings of the Korean Vacuum Society Conference
    • /
    • /
    • pp.79-79
    • /
    • 1999
  • The varous techniques for fabrication of si or metal tip as a field emission electron source have been reported due to great potential capabilities of flat panel display application. In this report, 240nm thermal oxide was initially grown at the p-type (100) (5-25 ohm-cm) 4 inch Si wafer and 310nm Si3N4 thin layer was deposited using low pressure chemical vapor deposition technique(LPCVD). The 2 micron size dot array was photolithographically patterned. The KOH anisotropic etching of the silicon substrate was utilized to provide V-groove formation. After formation of the V-groove shape, dry oxidation at 100$0^{\circ}C$ for 600 minutes was followed. In this procedure, the orientation dependent oxide growth was performed to have a etch-mask for dry etching. The thicknesses of the grown oxides on the (111) surface and on the (100) etch stop surface were found to be ~330nm and ~90nm, respectively. The reactive ion etching by 100 watt, 9 mtorr, 40 sccm Cl2 feed gas using inductively coupled plasma (ICP) system was performed in order to etch ~90nm SiO layer on the bottom of the etch stop and to etch the Si layer on the bottom. The 300 watt RF power was connected to the substrate in order to supply ~(-500)eV. The negative ion energy would enhance the directional anisotropic etching of the Cl2 RIE. After etching, remaining thickness of the oxide on the (111) was measured to be ~130nm by scanning electron microscopy.

  • PDF

Etch characteristics of TiN thin film adding $Cl_2$ in $BCl_3$/Ar Plasma ($BCl_3$/Ar 플라즈마에서 $Cl_2$ 첨가에 따른 TiN 박막의 식각 특성)

  • Um, Doo-Seung;Kang, Chan-Min;Yang, Xue;Kim, Dong-Pyo;Kim, Chang-Il
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • /
    • pp.168-168
    • /
    • 2008
  • Dimension of a transistor has rapidly shrunk to increase the speed of device and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate dioxide layer and low conductivity characteristic of poly-Si gate in nano-region. To cover these faults, study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$, and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-Si gate is not compatible with high-k materials for gate-insulator. Poly Si gate with high-k material has some problems such as gate depletion and dopant penetration problems. Therefore, new gate structure or materials that are compatible with high-k materials are also needed. TiN for metal/high-k gate stack is conductive enough to allow a good electrical connection and compatible with high-k materials. According to this trend, the study on dry etching of TiN for metal/high-k gate stack is needed. In this study, the investigations of the TiN etching characteristics were carried out using the inductively coupled $BCl_3$-based plasma system and adding $Cl_2$ gas. Dry etching of the TiN was studied by varying the etching parameters including $BCl_3$/Ar gas mixing ratio, RF power, DC-bias voltage to substrate, and $Cl_2$ gas addition. The plasmas were characterized by optical emission spectroscopy analysis. Scanning electron microscopy was used to investigate the etching profile.

  • PDF

Selective etching of SiO2 using embedded RF pulsing in a dual-frequency capacitively coupled plasma system

  • Yeom, Won-Gyun;Jeon, Min-Hwan;Kim, Gyeong-Nam;Yeom, Geun-Yeong
    • Proceedings of the Korean Vacuum Society Conference
    • /
    • /
    • pp.136.2-136.2
    • /
    • 2015
  • 반도체 제조는 chip의 성능 향상 및 단가 하락을 위해 지속적으로 pattern size가 nano size로 감소해 왔고, capacitor 용량은 증가해 왔다. 이러한 현상은 contact hole의 aspect ratio를 지속적으로 증가시킨바, 그에 따라 최적의 HARC (high aspect ratio contact)을 확보하는 적합한 dry etch process가 필수적이다. 그러나 HARC dry etch process는 많은 critical plasma properties 에 의존하는 매우 복잡한 공정이다. 따라서, critical plasma properties를 적절히 조절하여 higher aspect ratio, higher etch selectivity, tighter critical dimension control, lower P2ID과 같은 plasma characteristics을 확보하는 것이 요구된다. 현재 critical plasma properties를 제어하기 위해 다양한 plasma etching 방법이 연구 되어왔다. 이 중 plasma를 낮은 kHz의 frequency에서 on/off 하는 pulsed plasma etching technique은 nanoscale semiconductor material의 etch 특성을 효과적으로 향상 시킬 수 있다. 따라서 본 실험에서는 dual-frequency capacitive coupled plasma (DF-CCP)을 사용하여 plasma operation 동안 duty ratio와 pulse frequency와 같은 pulse parameters를 적용하여 plasma의 특성을 각각 제어함으로써 etch selectivity와 uniformity를 향상 시키고자 하였다. Selective SiO2 contact etching을 위해 top electrode에는 60 MHz pulsed RF source power를, bottom electrode에는 2MHz pulse plasma를 인가하여 synchronously pulsed dual-frequency capacitive coupled plasma (DF-CCP)에서의 plasma 특성과 dual pulsed plasma의 sync. pulsing duty ratio의 영향에 따른 etching 특성 등을 연구 진행하였다. 또한 emissive probe를 통해 전자온도, OES를 통한 radical 분석으로 critical Plasma properties를 분석하였고 SEM을 통한 etch 특성분석과 XPS를 통한 표면분석도 함께 진행하였다. 그 결과 60%의 source duty percentage와 50%의 bias duty percentage에서 가장 향상된 etch 특성을 얻을 수 있었다.

  • PDF

An Investigation of Selective Etching of GaAs to Al\ulcornerGa\ulcornerAs Using BCI$_3$SF\ulcorner Gas Mixture in ECR Plasma (ECR 플라즈마에서 $BCI_3/SF_6$ 혼합 가스를 이용한 $Al_{0.25}Ga_{0.75}As$에 대한 GaAs의 선택적 식각에 대한 연구)

  • 이철욱;이동율;손정식;배인호;박성배
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.11 no.6
    • /
    • pp.447-452
    • /
    • 1998
  • The selective dry etching of GaAs to Al\ulcornerGa\ulcornerAs using $BCI_3/SF_6$ gas mixture in electron cyclotron resonance(ECR) plasma is investigated. A selectivity of GaAs to AlGaAs of more than 100 and maximum etch rate of GaAs are obtained at a gas ratio $SF_6/BCI_3+SF_6$ of 25%. We verified the formation of $AlF_3$ on $Al_{0.25}Ga_{0.75}As$from the Auger spectra which enhanced the etch selectivity. In order to investigate surface damage of AlGaAs caused by ECR plasma, we performed a low temperature photoluminescence(PL) measurement as a function of RF power. As the RF power. As the RF power increases, the PL intensity decreases monotonically from 50 to 100 Wand then repidly decreases until 250 W. This behavior is due to surface damage by plasma treatment. This dry etching technique using $BCI_3/SF_6$ gas mixture in ECR plasma is suitable for gate recess formation on the GaAs based pseudomorphic high electron mobility transistor(PHEMT)

  • PDF

The Development of Cl-Plasma Etching Procedure for Si and SiO$_2$

  • Kim, Jong-Woo;Jung, Mi-Young;Park, Sung-Soo;Boo, Jin-Hyo
    • Journal of the Korean institute of surface engineering
    • /
    • v.34 no.5
    • /
    • pp.516-521
    • /
    • 2001
  • Dry etching of Si wafer and $SiO_2$ layers was performed using He/Cl$_2$ mixture plasma by diode-type reactive ion etcher (RIE) system. For Si etching, the Cl molecules react with the Si molecules on the surface and become chemically stable, indicating that the reactants need energetic ion bombardment. During the ion assisted desorption, energetic ions would damage the photoresist (PR) and produce the bad etch Si-profile. Moreover, we have examined the characteristics of the Cl-Si reaction system, and developed the new fabrication procedures with a $Cl_2$/He mixture for Si and $SiO_2$-etching. The developed novel fabrication procedure allows the RIE to be unexpensive and useful a Si deep etching system. Since the etch rate was proved to increase linearly with fHe and the selectivity of Si to $SiO_2$ etch rate was observed to be inversely proportional to fHe.

  • PDF

Etching of an Al Solid by SiCl$_4$ Molecules at 600 eV

  • Seung Chul Park;Chul Hee Cho;Chang Hwan Rhee
    • Bulletin of the Korean Chemical Society
    • /
    • v.11 no.1
    • /
    • pp.1-7
    • /
    • 1990
  • We present a theoretical investigation on the etching of an Al solid by $SiCl_4$ molecules at a collision energy of 600 eV. The classical trajectory method is employed to calculate Al etching yields, degree of anisotropy, kinetic energy distribution and angular distribution. The calculated results are compared with the reaction of a Cu solid by $SiCl_4$. The major products of the reaction are aluminum monomers and dimers together with considerable quantities of multimers. The Al solid shows better etching yield and better anisotropy than the Cu solid. This is consistent with the problem in the CMOS micro-fabrication of the CuAl and CuAlSi alloys. The relevance of these calculations for the dry etching of CuAl alloy is discussed.

  • PDF