• Title, Summary, Keyword: Dual Core System

Search Result 83, Processing Time 0.04 seconds

Implementation of the Shared Memory in the Dual Core System (Dual Core 시스템에서 Shared Memory 기능 구현)

  • Jang, Seung-Ju
    • The Journal of the Korea Contents Association
    • /
    • v.8 no.9
    • /
    • pp.27-33
    • /
    • 2008
  • This paper designs Shared Memory on the Dual Core system so that it operates a general System V IPC on the Linux O.S. Shared Memory is the technique that many processes can access to identical memory area. We treat Shared Memory which is SVR in a kernel step. We design a share memory facility of Linux operating system on the Dual Core System. In this paper the suggesting of share memory facility design plan in Dual Core system is enhance the performance in existing an unity processor system as a dual core practical use. We attemp a performance enhance in each CPU for each process which uses a share memory.

The Design of the Shared Memory in the Dual Core System (Dual Core 시스템에서 Shared Memory 기능 설계)

  • Jang, Seung-Ju;Lee, Gwang-Yong;Kim, Jae-Myeong
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.12 no.8
    • /
    • pp.1448-1455
    • /
    • 2008
  • This paper designs Shared Memory on the Dual Core system so that it operates a general System V IPC on the Linux O.S. Shared Memory is the technique that many processes can access to identical memory area. We treat Shared Memory in this paper among big two branches of Shared Memory which are SVR in a kernel step format. We design a share memory facility of Linux operating system on the Dual Core System. In this paper the suggesting design plan of share memory facility in Dual Core system is enhancing the performance in existing unity processor system as a dual core practical use. We attempt a performance enhance in each CPU for each process which uses a share memory.

Response Characteristic of the Dual-frame Passive Control System with the Natural Period Difference between the Strength Resistant Core and Frame Structure (강도저항형 코어와 프레임 구조의 진동주기차를 이용한 듀얼프레임 제진시스템의 응답특성)

  • Kim, Tae Kyung;Choi, Kwang Yong;Oh, Sang Hoon;Ryu, Hong Sik
    • Journal of the Earthquake Engineering Society of Korea
    • /
    • v.19 no.6
    • /
    • pp.273-282
    • /
    • 2015
  • In this study, shaking table test has been carried out for the dual frame passive control system for seismic performance verification of the proposed system. The proposed system was separated into two independent frameworks that are strength resistant core and frame structure by connecting to the damper. Moreover, the seismic performance improvement of the proposed system has been verified by comparing and analyzing the experimental results of the proposed system with an existing core system. As a result of the shaking table test, acceleration and displacement responses of dual-frame vibration control system are decreased than those of the existing strength resistant type core system. In the case of the core system, while the damage was concentrated on the column of first floor, the damage of the dual system was dispersed in each layer. The damage also was concentrated on the damper, almost no damage occurs to the structural members. It has been emphasized that installed dampers in the proposed dual system reduce the input energy of whole structure by absorbing seismic input energy, which leads overall system damage to be reduced.

Control Algorithm of Thyristor Dual Converter Power System for Railway Power Substations (철도 변전설비를 위한 싸이리스터 이중 컨버터 전력 시스템의 제어 기법)

  • Han, Sung-Woo;Lee, Chang-Hee;Kim, Young-Woo;Moon, Dong-Ok
    • The Transactions of the Korean Institute of Power Electronics
    • /
    • v.20 no.6
    • /
    • pp.573-579
    • /
    • 2015
  • A control algorithm of thyristor dual converter power system is proposed in this study for a railway power substation. The thyristor dual converter can use regenerative power without an additional system using control algorithm. An autonomous voltage and mode change method is also proposed to provide uninterrupted power to the railway. A 10 kW reduced model of the thyristor dual converter power system is built and tested to verify the validity of the proposed control algorithm.

Implementation of the Efficient Shared Memory in the Dual Core System (Dual Core 시스템에서 효율적인 공유 메모리 사용 기능 구현)

  • Jang, Seung Ju
    • Proceedings of the Korea Information Processing Society Conference
    • /
    • /
    • pp.543-544
    • /
    • 2009
  • 본 논문은 Linux에서 사용되는 Shared Memory는 동일한 메모리 영역에 여러 개의 프로세스가 접근할 수 있도록 해 주는 기술이다. 본 논문에서는 Shared Memory의 큰 두 갈래 중 커널 단계에서 처리 되는 SVR(System V Release) 형식의 Shared Memory를 다룬다. 본 논문에서는 리눅스 운영체제의 공유 메모리 기능을 Dual Core 시스템에서 동작하도록 구현한다.

  • PDF

Speed control system design using dual core DSP(TMS320F28377D) for the 2 Axis BLDC motor control (2축 BLDC 전동기 제어를 위한 듀얼코어 DSP(TMS320F28377D)를 이용하는 속도 제어 시스템 설계)

  • Lee, Dong-ju;Kim, Hee-chel;Lee, Dong-hyun;Choi, Jung-keyng
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • /
    • pp.232-234
    • /
    • 2017
  • In this research, the BLDC motor 2 axis controller was designed using a dual core processor. The controller used TMS320F28377D which is TI's latest dual-core DSP, and the BLDC motor was selected with the position of resolver having high reliavility and the speed sensor built-in type motor.

  • PDF

Parallel Control Algorithm of Thyristor Dual Converter Power System for DC Power Substation of Railway (철도 직류 급전용 싸이리스터 이중 컨버터 전력 시스템의 병렬운전 기법)

  • Kim, Young-Woo;Moon, Dong-Ok;Lee, Chang-Hee
    • The Transactions of the Korean Institute of Power Electronics
    • /
    • v.22 no.1
    • /
    • pp.9-17
    • /
    • 2017
  • A parallel control algorithm of thyristor dual-converter power system for the DC power supply of railway is proposed. The circulating current and current imbalance generated during parallel operation can be limited to control the output voltage of each power system by using the proposed parallel control algorithm. The proposed control algorithm can also eliminate output current sensor to achieve the same output response without additional costs. The validity of the proposed algorithm is verified through simulation and experiment.

Improvement Method and Performance Analysis of Shared Memory in Dual Core Embedded Linux system (듀얼코어 임베디드 리눅스 시스템에서 공유 메모리 성능 개선 방안 및 성능 분석)

  • Jung, Ji-Sung;Kim, Chang-Bong
    • Journal of Internet Computing and Services
    • /
    • v.11 no.4
    • /
    • pp.95-106
    • /
    • 2010
  • Recently multiple process communicate together. They share resource and information for cooperation in complicated programming environment. Kernel provides IPC (Inter -Process Communication) for communication with each other process. Shared Memory is a technique that many processes can access to identical memory area in the Linux environment. In this paper, we propose a performance improvement method of shared memory in the dual-core embedded linux system which is consist of different core and different operating system. We construct the MPC2530F (ARM926F+ARM946E) linux system and measure the performance therein. We attempt a performance enhancement in each CPU for each process which uses a shared memory.

Fabrication and Characterization of PLA Sheath-core Nanofibers by Coaxial Electrospinning (동축 전기방사를 통해 제조된 PLA Sheath-core 나노섬유의 제조 및 특성분석)

  • Kim, Min Hee;Kim, Hee Cheol;Park, Won Ho
    • Textile Science and Engineering
    • /
    • v.54 no.6
    • /
    • pp.456-461
    • /
    • 2017
  • In this study, poly(lactic acid) (PLA) nanofibers with sheath-core structure was prepared by coaxial electrospinning. The morphology of PLA sheath-core nanofibers was characterized using scanning electron microscopy (SEM) and confocal laser scanning microscopy (CLSM). The PLA nanofibers with sheath-core structure was successfully fabricated by coaxial electrospinning, and the loading of model drug was controlled by solution feed ratio. In addition, the dual drug release of PLA nanofibers was evaluated in the physiological media. From the results, the cumulative release rate of model drug in sheath part was higher than that in core part. The PLA sheath-core nanofibers has a great potential for drug delivery system and scaffolds for tissue engineering.

An Improving Method of Android Boot Speed in Multi-core based Embedded System (멀티코어 기반의 임베디드 시스템에서 안드로이드 부팅 속도 향상 방법)

  • Choi, Jin-Yong;Lee, Jae-Heung
    • Journal of IKEEE
    • /
    • v.17 no.4
    • /
    • pp.564-569
    • /
    • 2013
  • The current embedded devices are growing rapidly in the multi-core, and these demand fast boot time. But method of previous boot uses core only one. The method includes parallel techniques and modification of CPU Frequency policy. Parallel methods, after analyzing the Android boot process with analysis tool, applied to location where a lot of CPU operation. CPU Frequency policy is modified for high performance of core. The proposed method was applied to S5PV310 dual core and Exynos4412 quad core embedded system. As a result of the experiment, we found that the proposed method makes boot time fast about 20.71% and 31.34% in dual core and quad core environment as compared with the previous method.