• Title, Summary, Keyword: Element encryption

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The performance analysis of the selective element encryption method (선택적 요소 암호화 방식에 대한 성능 분석)

  • Yang, Xue;Kim, Ji-Hong
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.4
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    • pp.848-854
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    • 2015
  • There are a lot of encryption methods to secure database proposed recently. Those encryption methods can protect the sensitive data of users effectively, but it deteriorates the search performance of database query. In this paper, we proposed the selective element encryption method in order to complement those drawbacks. In addition, we compared the performance of the proposed method with that of tuple level encryption method using the various queries. As a result, we found that the proposed method, which use the selective element encryption with bloom filter as a index, has better performance than the other encryption method.

The Design of NPC Encryption Algorithms for Electronic Commerce (전자상거래를 위한 NPC 암호 알고리즘 설계)

  • 김재각;전문석
    • The Journal of Society for e-Business Studies
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    • v.6 no.2
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    • pp.159-166
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    • 2001
  • EC(Electronic Commerce) is increasing with high speed based on the expansion of Internet. EC which is done through Internet has strong point like independence from time and space, On the contrary, it also has weak point like security problem because anybody can access easily to the system due to open network attribute of Internet. Therefore, we need the solutions that protect the security problem for safe and useful U activity, One of these solutions is the implementation of strong cipher algorithm. NPC(Non-Polynomial Complete) cipher algorithm proposed in this paper is good for the security and it overcome the limit of current 64bits cipher algorithm using 256bits key for input output and encryption key, Moreover, it is designed for the increase of calculation complexity and probability calculation by adapting more complex design for subkey generation regarded as one of important element effected to encryption.

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An Implementation of 128bit Block Cipher Algorithm for Electronic Commerce (전자상거래를 위한 128비트 블록 암호 알고리즘의 구현)

  • 서장원;전문석
    • The Journal of Society for e-Business Studies
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    • v.5 no.1
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    • pp.55-73
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    • 2000
  • Recently; EC(Electronic Commerce) is increasing with high speed based on the expansion of Internet. EC which is done on the cyber space through Internet has strong point like independence from time and space. On the contrary, it also has weak point like security problem because anybody can access easily to the system due to open network attribute of Internet. Therefore, we need the solutions that protect the security problem for safe and useful EC activity. One of these solutions is the implementation of strong cipher algorithm. NC(Nonpolynomial Complete) cipher algorithm proposed in this paper is good for the security and it overcome the limit of current 64bits cipher algorithm using 128bits key length for input, output and encryption key, Moreover, it is designed for the increase of calculation complexity and probability calculation by adapting more complex design for subkey generation regarded as one of important element effected to encryption. The result of simulation by the comparison with other cipher algorithm for capacity evaluation of proposed NC cipher algorithm is that the speed of encryption and decryption is 7.63 Mbps per block and the speed of subkey generation is 2,42 μ sec per block. So, prosed NC cipher algorithm is regarded as proper level for encryption. Furthermore, speed of subkey generation shows that NC cipher algorithm has the probability used to MAC(Message Authentication Code) and block implementation of Hash function.

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A New Image Encryption Method using Quad-tree based Fresnelet Transform (쿼드트리 방식의 프레넬릿 변환을 이용한 영상의 암호화 기법)

  • Seo, Young-ho;Lee, Yoon-hyuk;Kim, Dong-wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.12
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    • pp.2933-2942
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    • 2015
  • This paper proposes a new method which traces significant element of 2-dimensional natural images and encrypts them by using Fresnelet transform (FRNLT). After analyzing property of the subbands obtained by the FRNLT, we estimated the information for ciphering 2D images. Considering FRNLT levels, energy of subbands, and visual effect, we estimated the optimized point for encryption. By selecting various levels and encrypting region, we can encrypt 2D image with various robustness. Encryption effectiveness was showed by analyzing numerical result, executing time for encryption, area of encrypted region, and visual observation. Therefore encryption for various application can be applied by using the suggested parameters without additional analysis. Identifying the experimental result, in the case of $L_{TH}=4$ and $L_{TH}=4$, an image was not recognized through encrypting only 0.42% among the entire data.

An Efficient Hardware Implementation of AES Rijndael Block Cipher Algorithm (AES Rijndael 블록 암호 알고리듬의 효율적인 하드웨어 구현)

  • 안하기;신경욱
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.12 no.2
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    • pp.53-64
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    • 2002
  • This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm, "Rijndael". An iterative looping architecture using a single round block is adopted to minimize the hardware required. To achieve high throughput rate, a sub-pipeline stage is added by dividing the round function into two blocks, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. The round block is implemented using 32-bit data path, so each sub-pipeline stage is executed for four clock cycles. The S-box, which is the dominant element of the round block in terms of required hardware resources, is designed using arithmetic circuit computing multiplicative inverse in GF($2^8$) rather than look-up table method, so that encryption and decryption can share the S-boxes. The round keys are generated by on-the-fly key scheduler. The crypto-processor designed in Verilog-HDL and synthesized using 0.25-$\mu\textrm{m}$ CMOS cell library consists of about 23,000 gates. Simulation results show that the critical path delay is about 8-ns and it can operate up to 120-MHz clock Sequency at 2.5-V supply. The designed core was verified using Xilinx FPGA board and test system.

An Implementation of YK2 Cipher System for Electronic Commerce Security (전자상거래 보안을 위한 YK2 암호시스템의 구현)

  • 서장원
    • The Journal of Society for e-Business Studies
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    • v.6 no.1
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    • pp.17-33
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    • 2001
  • EC(Electronic Commerce) which is done on the virtual space through Internet has strong point like independence from time and space. On the contrary, it also has weak point like security problem because anybody can access easily to the system due to open network attribute of Internet, Therefore, we need the solutions that protect the EC security problem for safe and useful EC activity. One of these solutions is the implementation of strong cipher system. YK2(Young Ku King) cipher system proposed in this paper is good solution for the EC security and it overcome the limit of current block cipher system using 128 bits key length for input, output, encryption key and 32 rounds. Moreover, it is designed for the increase of time complexity by adapting more complex design for key scheduling algorithm regarded as one of important element effected to encryption.

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A Study on Web Security using NC Cipher System (NC 암호시스템을 이용한 웹 보안에 관한 연구)

  • 서장원;전문석
    • Proceedings of the IEEK Conference
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    • pp.55-58
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    • 2000
  • EC, which is done the virtual space through Web, has weakly like security problem because anybody can easily access to the system due to open network attribute of Web. Therefore, we need the solutions that protect the Web security for safe and useful EC. One of these solutions is the implementation of a strong cipher system. NC(Nonpolynomial Complete) cipher system proposed in this paper is advantage for the Web security and it overcomes the limit of the 64 bits cipher system using 128 bits key length for input, output, encryption key and 16 rounds. Moreover, it is designed for the increase of time complexity by adapted more complex design for key scheduling regarded as one of the important element effected to encryption.

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A Study on Cooperation between Kerberos system and Credit-Control Server

  • Choi, Bae-Young;Lim, Hyung-Jin;Chung, Tai-Myoung
    • Proceedings of the Korea Society of Information Technology Applications Conference
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    • pp.281-284
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    • 2005
  • Kerberos is system that offer authorization in internet and authentication service. Can speak that put each server between client and user in distributed environment and is security system of symmetry height encryption base that offer authentication base mutually. Kerberos authentication is based entirely on the knowledge of passwords that are stored on the Kerberos Server. A user proves her identity to the Kerberos Server by demonstrating Knowledge of the key. The fact that the Kerberos Server has access to the user's decrypted password is a rwsult of the fact that Kerberos does not use public key cryptogrphy. It is a serious disadvantage of the Kerbercs System. The Server must be physically secure to prevent an attacker from stealing the Kerberos Server and learning all of the user passwords. Kerberos was designend so that the server can be stateless. The Kerberos Server simply answers requests from users and issues tickets. This study focused on designing a SIP procy for interworking with AAA server with respect to user authentication and Kerberos System. Kerberos is security system of encryption base that offer certification function mutually between client application element and server application element in distributed network environment. Kerberos provides service necessary to control whether is going to approve also so that certain client may access to certain server. This paper does Credit-Control Server's function in AAA system of Diameter base so that can include Accounting information that is connected to Rating inside certification information message in Rating process with Kerberos system.

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Definition and Generation of Level 0 Product for KOMPSAT-2

  • Shin, Ji-Hyeon;Kim, Moon-Gyu;Park, Sung-Og
    • Proceedings of the KSRS Conference
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    • pp.810-814
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    • 2002
  • According to the image level definition for KOMPSAT-2 in KOMPSAT-2 Ground Station Specification, the level 0 is frame formatted, unprocessed data at full resolution; any and all communications artifacts (e.g., synchronization frames, communications headers) removed. The level 0 is used for two purposes: 1) exchange of imagery between image receiving & processing element (IRPE), and 2) image transfer from the Receiving & Archiving Subsystem to Search & Processing Subsystem. On-board processing of imagery data of KOMPSAT-2 includes JPEG-like compression and encryption besides conventional CCSDS packetization. The encryption is used to secure imagery data from any intervention during downlink and compression allows real-time downlink of image data reducing data rate produced from the camera. While developing ground receiving system for KOMPSAT-2, it was necessarily to define level 0 products. In this paper, we will suggest level 0 product definition for KOMPSAT-2 and explain reasons of the decisions made. The key factor used while defining the level 0 products is the efficiency of whole ground receiving system. The latter half of the paper will explain the implementation of software that generates level 0 products. The necessary steps to produce level 0 products will be explained, and the performance achieved will be presented.

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Implementation of High-radix Modular Exponentiator for RSA using CRT (CRT를 이용한 하이래딕스 RSA 모듈로 멱승 처리기의 구현)

  • 이석용;김성두;정용진
    • Journal of the Korea Institute of Information Security & Cryptology
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    • v.10 no.4
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    • pp.81-93
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    • 2000
  • In a methodological approach to improve the processing performance of modulo exponentiation which is the primary arithmetic in RSA crypto algorithm, we present a new RSA hardware architecture based on high-radix modulo multiplication and CRT(Chinese Remainder Theorem). By implementing the modulo multiplier using radix-16 arithmetic, we reduced the number of PE(Processing Element)s by quarter comparing to the binary arithmetic scheme. This leads to having the number of clock cycles and the delay of pipelining flip-flops be reduced by quarter respectively. Because the receiver knows p and q, factors of N, it is possible to apply the CRT to the decryption process. To use CRT, we made two s/2-bit multipliers operating in parallel at decryption, which accomplished 4 times faster performance than when not using the CRT. In encryption phase, the two s/2-bit multipliers can be connected to make a s-bit linear multiplier for the s-bit arithmetic operation. We limited the encryption exponent size up to 17-bit to maintain high speed, We implemented a linear array modulo multiplier by projecting horizontally the DG of Montgomery algorithm. The H/W proposed here performs encryption with 15Mbps bit-rate and decryption with 1.22Mbps, when estimated with reference to Samsung 0.5um CMOS Standard Cell Library, which is the fastest among the publications at present.

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