• Title, Summary, Keyword: Encoder design

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New Efficient Design of Reed-Solomon Encoder, Which has Arbitrary Parity Positions, without Galois Field Multiplier

  • An, Hyeong-Keon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.6B
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    • pp.984-990
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    • 2010
  • In Current Digital $C^3$ Devices(Communication, Computer, Consumer electronic devices), Reed-Solomon encoder is essentially used. For example we should use RS encoder in DSP LSI of CDMA Mobile and Base station modem, in controller LSI of DVD Recorder and that of computer memory(HDD or SSD memory). In this paper, we propose new economical multiplierless (also without divider) RS encoder design method. The encoder has Arbitrary parity positions.

Design and Development of a Novel High Resolution Absolute Rotary Encoder System Based on Affine n-digit N-ary Gray Code

  • Paul, Sarbajit;Chang, Junghwan
    • Journal of Electrical Engineering and Technology
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    • v.13 no.2
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    • pp.943-952
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    • 2018
  • This paper presents a new type of absolute rotary encoder system based on the affine n-digit N-ary gray code. A brief comparison of the existing encoder systems is carried out in terms of resolution, encoding and decoding principles and number of sensor heads needed. Using the proposed method, two different types of encoder disks are designed, namely, color-coded disk and grayscale coded disk. The designed coded disk pattern is used to manufacture 3 digit 3 ary and 2 digit 5 ary grayscale coded disks respectively. The manufactured disk is used with the light emitter and photodetector assembly to design the entire encode system. Experimental analysis is done on the designed prototype with LabVIEW platform for data acquisition. A comparison of the designed system is done with the traditional binary gray code encoder system in terms of resolution, disk diameter, number of tracks and data acquisition system. The resolution of the manufactured system is 3 times higher than the conventional system. Also, for a 5 digit 5 ary coded encoder system, a resolution approximately 100 times better than the conventional binary system can be achieved. In general, the proposed encoder system gives $(N/2)^n$ times better resolution compared with the traditional gray coded disk. The miniaturization in diameter of the coded disk can be achieved compared to the conventional binary systems.

Design and Construction of a Surface Encoder with Dual Sine-Grids

  • Kimura, Akihide;Gao, Wei;Kiyono, Satoshi
    • International Journal of Precision Engineering and Manufacturing
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    • v.8 no.2
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    • pp.20-25
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    • 2007
  • This paper describes a second-generation dual sine-grid surface encoder for 2-D position measurements. The surface encoder consisted of a 2-D grid with a 2-D sinusoidal pattern on its surface, and a 2-D angle sensor that detected the 2-D profile of the surface grid The 2-D angle sensor design of previously developed first-generation surface encoders was based on geometric optics. To improve the resolution of the surface encoder, we fabricated a 2-D sine-grid with a pitch of $10{\mu}m$. We also established a new optical model for the second-generation surface encoder that utilizes diffraction and interference to generate its measured values. The 2-D sine-grid was fabricated on a workpiece by an ultra precision lathe with the assistance of a fast tool servo. We then performed a UV-casting process to imprint the sine-grid on a transparent plastic film and constructed an experimental setup to realize the second-generation surface encoder. We conducted tests that demonstrated the feasibility of the proposed surface encoder model.

Design of XML Using UML in EtherCAT-based Encoder System (EtherCAT 기반 엔코더 시스템에서 UML을 이용한 XML 설계)

  • Lee, Ju-Kyoung;Lee, Suk;Lee, Kyung-Chang
    • IEMEK Journal of Embedded Systems and Applications
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    • v.9 no.2
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    • pp.117-125
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    • 2014
  • The EtherCAT protocol has become a very promising alternative for real-time industrial application due to its ability to eliminate uncertainties in the Ethernet. However, the extended markup language (XML) for the EtherCAT network system, which is required in the design, lacks systematic development to take advantage of model transformation techniques. This paper focuses on the system development procedure of the EtherCAT-based encoder system using the CANopen over EtherCAT (CoE) protocol. UML modeling is being adapted to design for XML of EtherCAT-based encoder system. To this purpose, this paper analyzes the object dictionary (OD) of a commercial encoder and CANopen over EtherCAT. A UML diagram is then designed based on the analysis, and XML is generated through the designed UML diagram. Finally, an experimental test_bed for the EtherCAT-based encoder system is implemented and its performance is compared with a commercial encoder.

A Design of A Multistandard Digital Video Encoder using a Pipelined Architecture

  • Oh, Seung-Ho;Park, Han-Jun;Kwon, Sung-Woo;Lee, Moon-Key
    • Journal of Electrical Engineering and information Science
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    • v.2 no.5
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    • pp.9-16
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    • 1997
  • This paper describes the design of a multistandard video encoder. The proposed encoder accepts conventional NTSC/PAL video signals, It also processes he PAL-plus video signal which is now popular in Europe. The encoder consists of five major building functions which are letter-box converter, color space converter, digital filters, color modulator and timing generator. In order to support multistandard video signals, a programmable systolic architecture is adopted in designing various digital filters. Interpolation digital filters are also used to enhance signal-to-noise ratio of encoded video signals. The input to the encoder can be either YCbCr signal or RGB signal. The outputs re luminance(Y), chrominance(C), and composite video baseband(Y+C) signals. The architecture of the encoder is defined by using Matlab program and is modelled by using Veriflog-HDL language. The overall operation is verified by using various video signals, such as color bar patterns, ramp signals, and so on. The encoder contains 42K gates and is implemented by using 0.6um CMOS process.

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A Design of Direct Memory Access (DMA) Controller For H.264 Encoder (H.264 Encoder용 Direct Memory Access (DMA) 제어기 설계)

  • Song, In-Keun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.14 no.2
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    • pp.445-452
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    • 2010
  • In this paper, an attempt has been made to design the controller applicable for H.264 level3 encoder of baseline profile on full hardware basis. The designed controller module first stores the images supplied from CMOS Image Sensor(CIS) at main memory, and then reads or stores the image data in macroblock unit according to encoder operation. The timing cycle of the DMA controller required to process a macroblock is 478 cycles. In order to verify the our design, reference-C encoder, which is compatible to JM 9.4, is developed and the designed controller is verified by using the test vector generated from the reference C code. The number of cycle in the designed DMA controller is reduced by 40% compared with the cycle of using Xilinx MIG.

System-level Function and Architecture Codesign for Optimization of MPEG Encoder

  • Choi, Jin-Ku;Togawa, Nozomu;Yanagisawa, Masao;Ohtsuki, Tatsuo
    • Proceedings of the IEEK Conference
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    • pp.1736-1739
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    • 2002
  • The advanced in semiconductor, hardware, and software technologies enables the integration of more com- plex systems and the increasing design complexity. As system design complexity becomes more complicated, System-level design based on the If block and processor model is more needed in most of the RTL level or low level. In this paper, we present a novel approach fur the system-level design, which satisfies the various required constraints and an optimization method of image encoder based on codesign of function, algorithm, and architecture. In addition, we show an MPEG-4 encoder as a design case study. The best tradeoffs between algorithm and architecture are necessary to deliver the design with satisfying performance and area constraints. The evaluations provide the effective optimization of motion estimation, which is in charge of an amount of performance in the MPEG-4 encoder module.

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Design and Implementation of the Manchester Encoder for RFID (RFID용 Manchester Encoder의 설계 및 구현)

  • Kim Ki-Ho;Kim Jae-Hyung;Park Hyung-Moo
    • Proceedings of the IEEK Conference
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    • pp.525-528
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    • 2004
  • Manchester encoder of FSM method is a suitable signal coding for an RFID system. However, Manchester encoder of FSM method has usually more gate count and lower maximum frequency than encoder of exclusive-OR gate method. In this paper. it is proposed encoder of FSM method to improve gate count and maximum frequency.

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The Encoder Design of Punctured Turbo Trellis Coded Modulation applied to MPSK

  • Seon, Wang-Seok;Kim, Youn-Hyoung;Lee, Ho-Kyung
    • Proceedings of the IEEK Conference
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    • pp.2071-2074
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    • 2002
  • This paper introduces an encoder design method of Turbo TCM (Trellis Coded Modulation) with symbol puncturing. TTCM consists of two simple trellis codes in parallel and modulator. To obtain an good encoder, we calculate the free distance by the assumption that the punctured symbol is transmitted from the subset that consist of signals with the same systematic bit at random. We develop a search program to find the component encoder which maximize the free distance. Especially, for 8-PSK with code rate 2/3, we search for the component codes. We find a new encoder which has better BER performance than that of Robertson′s encoder. We verify the results through the simulation."

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On Top-Down Design of MPEG-2 Audio Encoder

  • Park, Sung-Wook
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.8 no.1
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    • pp.75-81
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    • 2008
  • This paper presents a top-down approach to implement an MPEG-2 audio encoder in VLSI. As the algorithm of an MPEG-2 audio encoder is heavy-weighted and heterogeneous(to be mixture of several strategies), the encoder design process is undertaken carefully from the algorithmic level to the architectural level. Firstly, the encoding algorithm is analyzed and divided into sub-algorithms, called tasks, and the tasks are partitioned in the way of reusing the same designs. Secondly, the partitioned tasks are scheduled and synthesized to make the most efficient use of time and space. In the end, a real-time 5 channel MPEG-2 audio encoder is designed which is a heterogeneous multiprocessor system; two hardwired logic blocks and one specialized DSP processor.