• Title, Summary, Keyword: FTL

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Janus-FTL Adjusting the Size of Page and Block Mapping Areas using Reference Pattern (참조 패턴에 따라 페이지 및 블록 사상 영역의 크기를 조절하는 Janus-FTL)

  • Kwon, Hun-Ki;Kim, Eun-Sam;Choi, Jong-Moo;Lee, Dong-Hee;Noh, Sam-H.
    • Journal of KIISE:Computing Practices and Letters
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    • v.15 no.12
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    • pp.918-922
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    • 2009
  • Naturally, block mapping FTL works well for sequential writes while page mapping FTL does well for random writes. To exploit their advantages, a practical FTL should be able to selectively apply a suitable scheme between page and block mappings for each write pattern. To meet that requirement, we propose a hybrid mapping FTL, which we call Janus-FTL, that distributes data to either block or page mapping areas. Also, we propose the fusion operation to relocate the data from block mapping area to page mapping area and the defusion operation to relocate the data from page mapping area to block mapping area. And experimental results of Janus-FTL show performance improvement of maximum 50% than other hybrid mapping FTLs.

An Efficient FTL Algorithm for Flash Memory (플래시 메모리를 위한 효율적인 사상 알고리즘)

  • Chung Tae-Sun;Park Hyung-Seok
    • Journal of KIISE:Computer Systems and Theory
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    • v.32 no.9
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    • pp.483-490
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    • 2005
  • Recently, flash memory is widely used in embedded applications since it has strong points: non-volatility, fast access speed, shock resistance, and low power consumption. However, due to its hardware characteristics, it requires a software layer called FTL(flash translation layer). The main functionality of FTL is to convert logical addresses from the host to physical addresses of flash memory We present a new FTL algorithm called STAFF(State Transition Applied Fast Flash Translation Layer). Compared to the previous FTL algorithms, STAFF shows five times higher performance than basic block mapping scheme and requires less memory. We provide performance results based on our implementation of STAFF and previous FTL algorithms.

IPSiNS: I/O Performance Simulation Tool for NAND Flash Memory-based Storage System (IPSiNS: 낸드 플래시 메모리 기반 저장 장치를 위한 입출력 성능 시뮬레이션 도구)

  • Yoon, Kyeong-Hoon;Jung, Ho-Young;Park, Sung-Min;Sim, Hyo-Gi;Cha, Jae-Hyuk;Kang, Soo-Yong
    • Journal of KIISE:Computing Practices and Letters
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    • v.13 no.5
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    • pp.333-337
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    • 2007
  • Flash Translation Layer(FTL) which enables NAND Flash memory-based storage system to be used as a block device is designed considering only characteristics of NAND Flash memory. However, since FTL precesses I/O requests which survived against buffer replacement algorithm, FTL algorithm has tight relationship with buffer replacement algorithm. Therefore, if we do not consider both FTL and buffer replacement algorithms, it is difficult to predict the actual I/O performance of the computer systems that have Flash memory-based storage system. The necessity of FTL and buffer replacement algorithm co-design arises here. In this work, we implemented I/O performance evaluation tool, IPSiNS, which simulates both the buffer replacement and FTL algorithms, simultaneously.

An Offline FTL Algorithm to Verify the Endurance of Flash SSD (플래시 SSD의 내구성을 검증하기 위한 FTL 오프라인 알고리즘)

  • Jung, Ho-Young;Lee, Tae-Hwa;Cha, Jae-Hyuk
    • Journal of Digital Contents Society
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    • v.13 no.1
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    • pp.75-81
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    • 2012
  • SSDs(Solid State Drives) have many attractive features such as high performance, low power consumption, shock resistance, and low weight, so they replace HDDs to a certain extent. An SSD has FTL(Flash Translation Layer) which emulate block storage devices like HDDs. A garbage collection, one of major functions of FTL, effects highly on the performance and the lifetime of SSDs. However, there is no de facto standard for new garbage collection algorithms. To solve this problem, we propose trace driven offline optimal algorithms for garbage collection of FTL. The proposed algorithm always guarantees minimal number of erase operation. In addition, we verify our proposed algorithm using TPC trace.

Development of Simulator using RAM Disk for FTL Performance Analysis (RAM 디스크를 이용한 FTL 성능 분석 시뮬레이터 개발)

  • Ihm, Dong-Hyuk;Park, Seong-Mo
    • Journal of the Institute of Electronics Engineers of Korea CI
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    • v.47 no.5
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    • pp.35-40
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    • 2010
  • NAND flash memory has been widely used than traditional HDD in PDA and other mobile devices, embedded systems, PC because of faster access speed, low power consumption, vibration resistance and other benefits. DiskSim and other HDD simulators has been developed that for find improvements for the software or hardware. But there is a few Linux-based simulators for NAND flash memory and SSD. There is necessary for Windows-based NAND flash simulator because storage devices and PC using Windows. This paper describe for development of simulator-NFSim for FTL performance analysis in NAND flash. NFSim is used to measure performance of various FTL algorithms and FTL wear-level. NAND flash memory model and FTL algorithm developed using Windows Driver Model and class for scalability. There is no need for another tools because NFSim using graph tool for data measure of FTL performance.

Performance Analysis of Flash Translation Layer Algorithms for Windows-based Flash Memory Storage Device (윈도우즈 기반 플래시 메모리의 플래시 변환 계층 알고리즘 성능 분석)

  • Park, Won-Joo;Park, Sung-Hwan;Park, Sang-Won
    • Journal of KIISE:Computing Practices and Letters
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    • v.13 no.4
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    • pp.213-225
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    • 2007
  • Flash memory is widely used as a storage device for potable equipments such as digital cameras, MP3 players and cellular phones because of its characteristics such as its large volume and nonvolatile feature, low power consumption, and good performance. However, a block in flash memories should be erased to write because of its hardware characteristic which is called as erase-before-write architecture. The erase operation is much slower than read or write operations. FTL is used to overcome this problem. We compared the performance of the existing FTL algorithms on Windows-based OS. We have developed a tool called FTL APAT in order to gather I/O patterns of the disk and analyze the performance of the FTL algorithms. It is the log buffer scheme with full associative sector translation(FAST) that the performance is best.

SQLite Multi-version Concurrency Control using X-FTL (X-FTL 을 활용한 SQLite 다중버전 동시성 제어)

  • Lee, Jong-Baeg;Oh, Gi-Hwan;Lee, Sang-Won
    • Proceedings of the Korea Information Processing Society Conference
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    • pp.794-797
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    • 2014
  • 스마트 디바이스의 사용량 증가와 더불어 각종 가전기기의 스마트화로 인하여 임베디드 시스템에서 주로 사용되는 SQLite 데이터베이스에 대한 동시적 접근 제어의 중요성이 증가하였다. 플래시 메모리 저장장치 단계에서 트랜잭션의 원자성올 제공하는 X-FTL 은 SQLite 의 저널링 모드에서 발생하는 쓰기 연산으로 인한 성능 저하를 해결하였다. 또한 페이지 단위로 트랜잭션의 원자성을 관리하는 X-FTL 의 특징을 이용한다면 동시성 제어 측면의 성능 향상을 기대할 수 있다. 본 논문에서는 X-FTL 을 사용할 때 발생할 수 있는 동시성 제어 성능의 한계를 밝히고, X-FTL 의 X-L2P 테이블에 SCN 을 추가하여 SQLite 의 동시성 제어 성능을 향상할 수 있는 새로운 구조를 제안한다.

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Fault Tolerant FTL Gaits for Walking over Irregular Terrain (비평탄 지형 보행을 위한 내고장성 FTL 걸음새)

  • Yang Jung-Min
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.43 no.3
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    • pp.16-24
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    • 2006
  • In this paper, fault-tolerant gait planning of a hexapod robot for walking over irregular terrain is presented. The failure concerned in this paper is a locked joint failure for which a joint in a leg cannot move and is locked in place. Based on the previously proposed fault-tolerant tripod gait for walking over even terrain, fault-tolerant follow-the-leader(FTL) gaits are proposed for a hexapod robot with a failed leg to be able to walk over two-dimensional rough terrain, maintaining static stability and fault tolerance. The proposed FTL gait can have maximum stride length for a given foot position of a failed leg, and yields better ditch crossing ability than the previously developed gaits. The applicability of the proposed FTL gait is verified by using computer graphics simulations.

Performance Analysis of Flash Translation Layer using TPC-C Benchmark (플래시 변환 계층에 대한 TPC-C 벤치마크를 통한 성능분석)

  • Park, Sung-Hwan;Jang, Ju-Yeon;Suh, Young-Ju;Park, Won-Joo;Park, Sang-Won
    • Journal of KIISE:Computing Practices and Letters
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    • v.14 no.2
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    • pp.201-205
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    • 2008
  • The flash memory is widely used as a main storage of embedded devices. It is adopted as a storage of database as growing the capacity of the flash memory. We run TPC-C benchmark on various FTL algorithms. But, the database shows poor performance on flash memory because the characteristic of I/O requests is full random. In this paper, we show the performance of all existing FTL algorithms is very poor. Especially, the FTL algorithm known as good at small mobile equipment shows worst performance. In addition, the chip-inter leaving which is a technique to improve the performance of the flash memory doesn't work well. In this paper, we inform you the reason that we need a new FTL algorithm and the direction for the database in the future.

An Efficient System Software of Flash Translation Layer for Large Block Flash Memory (대용량 플래시 메모리를 위한 효율적인 플래시 변환 계층 시스템 소프트웨어)

  • Chung Tae-Sun;Park Dong-Joo;Cho Sehyeong
    • The KIPS Transactions:PartA
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    • v.12A no.7
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    • pp.621-626
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    • 2005
  • Recently, flash memory is widely used in various embedded applications since it has many advantages in terms of non-volatility, fast access speed, shock resistance, and low power consumption. However, it requires a software layer called FTL(Flash Translation Layer) due to its hardware characteristics. We present a new FTL algorithm named LSTAFF(Large State Transition Applied Fast flash Translation Layer) which is designed for large block flash memory The presented LSTAFF is adjusted to flash memory with pages which are larger than operating system data sector sizes and we provide performance results based on our implementation of LSTAFF and previous FTL algorithms using a flash simulator.