• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.1089-1095
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• 2004

The genetic algorithms have been used to take a near optimal solution because The generation of the optimal Steiner tree from a given network is NP-hard problem,. The chromosomes in genetic algorithm are represented with the floating point representation instead of the existing binary string for solving this problem. A spanning tree was obtained from a given network using Prim's algorithm. Then, the new Steiner point was computed using genetic algorithm with the chromosomes in the floating point representation, and it was added to the tree for approaching the result. After repeating these evolving steps, the near optimal Steiner tree was obtained. Using this method, the tree is quickly and exactly approached to the near optimal Steiner tree compared with the existing genetic algorithms using binary string.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.2
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• pp.428-431
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• 2007

A floating-point number system is used to represent a wide range of real numbers using finite number of bits. The standard the IEEE adopted in 1987 divides the range of real numbers into intervals of [$2^E,2^{E+1}$), where E is an Integer represented with finite bits, and defines equally spaced equal counts of discrete numbers in each interval. Since the numbers are defined discretely, not only the number representation itself includes errors but in floating-point arithmetic some strange behaviors are observed which cannot be agreed with the real world arithmetic. In this paper errors with floating-point number representation, those with arithmetic operations, and those due to order of arithmetic operations are analyzed theoretically with help of and verification with the results of some MATLAB program executions.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.3
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• pp.96-105
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• 1992

The use of fixed-point digital signal processors, such as the TMS 320C25, requires scaling of data at each arithmetic step to prevent overflows while keeping the accuracy. A software which automatizes this process is developed for TMS 320C25. The programmers use a model of a hypothetical floating-point digital signal processor and a floating-point format for data representation. However, the program and data are automatically translated to a fixed-point version by this software. Thus, the execution speed is not sacrificed. A fixed-point variable has a unique binary-point location, which is dependent on the range of the variable. The range is estimated from the floating-point simulation. The number of shifts needed for arithmetic or data transfer step is determined by the binary-points of the variables associated with the operation. A fixed-point code generator is also developed by using the proposed automatic scaling software. This code generator produces floating-point assembly programs from the specifiations of FIR, IIR, and adaptive transversal filters, then floating-point programs are transformed to fixed-point versions by the automatic scaling software.

• Journal of the Society of Naval Architects of Korea
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• v.35 no.4
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• pp.118-125
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• 1998

This paper presents the hybrid curve approximation with geometric boundary conditions as position vector and tangent vector of start and end point using a B-spline approximation and a genetic algorithm First, H-spline approximation generates control points to fit B-spline curries through specified data points. Second, these control points are modified by genetic algorithm(with floating point representation) under geometric boundary conditions. This method would be able to execute the efficient design work without fairing.

• Proceedings of the IEEK Conference
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• pp.723-724
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• 2008

In this paper, we explore face recognition technology for embedded system. We develop an algorithm suitable for systems under ubiquitous environment. The basic requirements includes appropriate data format and ratio of feature data to achieve efficiency of algorithm. Our experiment presents a face recognition technique for handheld devices. The essential parts for face recognition based on embedded system includes; integer representation from floating point calculation and optimization for memory management.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.6
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• pp.314-321
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• 2019

The Self-Adaptive Vision Correction Algorithm (SAVCA) developed in this study was suggested for improving usability by modifying four parameters (Modulation Transfer Function Rate, Astigmatic Rate, Astigmatic Factor and Compression Factor) except for Division Rate 1 and Division Rate 2 among six parameters in Vision Correction Algorithm (VCA). For verification, SAVCA was applied to two-dimensional mathematical benchmark functions (Six hump camel back / Easton and fenton) and 30-dimensional mathematical benchmark functions (Schwefel / Hyper sphere). It showed superior performance to other algorithms (Harmony Search, Water Cycle Algorithm, VCA, Genetic Algorithms with Floating-point representation, Shuffled Complex Evolution algorithm and Modified Shuffled Complex Evolution). Finally, SAVCA showed the best results in the engineering problem (speed reducer design). SAVCA, which has not been subjected to complicated parameter adjustment procedures, will be applicable in various fields.

• Journal of IKEEE
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• v.22 no.3
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• pp.805-809
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• 2018

In this paper, we analyze the change of accuracy when fixed point arithmetic is used instead of floating point arithmetic in binary weight network(BWN). We observed the change of accuracy by varying total bit size and fraction bit size. If the integer part is not changed after fixed point approximation, there is no significant decrease in accuracy compared to the floating-point operation. When overflow occurs in the integer part, the approximation to the maximum or minimum of the fixed point representation minimizes the decrease in accuracy. The results of this paper can be applied to the minimization of memory and hardware resource requirement in the implementation of FPGA-based BWN accelerator.

• KIPS Transactions on Software and Data Engineering
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• v.2 no.11
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• pp.809-814
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• 2013

Summed area table (SAT) is a data structure in which the sum of pixel values in an arbitrary rectangular area can be represented by the linear combination of four pixel values. Since SAT serially accumulates the pixel values from an image corner to the other corner, a high-resolution image can yield overflow in a floating-point representation. In this paper, we present a new SAT construction technique, which accumulates only the residuals from the linearly-regressed representation of an image and thereby significantly reduces the accumulation errors. Also, we propose a method to find the integral of the linear regression in constant time using double integral. We performed experiments on the image reconstruction, and the results showed that our approach more reduces the accumulation errors than the conventional fixed-offset SAT.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.12
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• pp.723-731
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• 2005

The $4{\times}4$ homogeneous transformation matrix is a compact representation of orientation and position of an object in robotics and computer graphics. A coordinate transformation is accomplished through the successive multiplications of homogeneous matrices, each of which represents the orientation and position of each corresponding link. Thus, for real time control applications in robotics or animation in computer graphics, the fast multiplication of homogeneous matrices is quite demanding. In this paper, a parallel-architecture vector processor is designed for this purpose. The processor has several key features. For the accuracy of computation for real application, the operands of the processors are floating point numbers based on the IEEE Standard 754. For the parallelism and reduction of hardware redundancy, the processor takes column vectors of homogeneous matrices as multiplication unit. To further improve the throughput, the processor structure and its control is based on a pipe-lined structure. Since the designed processor can be used as a special purpose coprocessor in robotics and computer graphics, additionally to special matrix/matrix or matrix/vector multiplication, several other useful instructions for various transformation algorithms are included for wide application of the new design. The suggested instruction set will serve as standard in future processor design for Robotics and Computer Graphics. The design is verified using FPGA implementation. Also a comparative performance improvement of the proposed design is studied compared to a uni-processor approach for possibilities of its real time application.

• Journal of Energy Engineering
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• v.6 no.1
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• pp.11-18
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• 1997

This paper describes a daily operation scheduling of cogeneration systems using Genetic Algorithm. The simulation was performed in the case of bottoming cycle. The efficiency of cogeneration system which has nonlinear characteristic is obtained by the least square method based on the real data of industrial cogeneration system. In this paper, Genetic Algorithm is coded as a vector of floating point representation which can reduce computation time and obtain high precision The simulated results show that the genetic algorithm can be efficiently applied to establish the operation scheduling.